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Design Of Low Power Speculative Han-Carlson Adder

Publication Type : Journal Article

Publisher : International Journal For Trends In Engineering And Technology

Source : International Journal For Trends In Engineering And Technology (2016)

Campus : Bengaluru

School : School of Engineering

Center : Electronics Communication and Instrumentation Forum (ECIF)

Department : Electronics and Communication

Verified : Yes

Year : 2016

Abstract : Low power and high speed design is one of the important building blocks in digital circuits. In conventional Inexact speculative adder based on Carry look-ahead adder to consume more power issues and longest critical path delay. In this paper, Han Carlson adder based design of the proposed ISA architecture which is fine grain pipelined because to increase the processing speed and reduces the complexity, silicon area and power consumption. Additionally this architecture has been clock gated giving rise to dynamic power reduction opportunity. Functional verification and synthesis of suggested ISA is carried out on 45nm CMOS technology by using Tanner EDA tool. Index Terms-Inexact speculative adder(ISA), Han Carlson adder(HCA), Pipelining, clock gated.

Cite this Research Publication : Kamatchi S., “Design Of Low Power Speculative Han-Carlson Adder”, International Journal For Trends In Engineering And Technology, 2016.

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