Syllabus
Unit 1
Scaling Trends and Methodologies, Motivation for continued scaling of device dimensions, ITRS Road map, Si and GaAs Structure, Properties, Crystalline Directions, Sand to Silicon, Single Crystal Growth – CZ – Float Zone growth – Bridgman Growth, CMP & Polishing of Si Ingot, Gettering; Thermal Oxidation Process – Deal Groove Model – Linear and Parabolic Rate Coefficients – Oxide Characterization; Photolithography – Optical Lithography – Positive/ Negative Photoresists, Photo Masks, Types of Pattern Transfer, Diffraction Limits – Rayleigh Criterion, Light sources
Unit 2:
Extreme UV Lithography, Modulation Transfer Function, Spatial Coherence, Advanced Mask Techniques – Phase shift mask, Optical proximity correction, Antireflective coating; Photoresists – Components of Resist, DQN Photoresist, Resist Contrast and Critical Modulation Transfer Function, Resists for EUV lithography; Etching – Etch Metrics – Wet Chemical Etching – Plasma Assisted Etching – RIE – High Density Plasma – DRIE process – CMP; Ion Implantation – process and system – Mass Analyzer – Ion Stopping – Implantation Profile and control – Deviations from Gaussian Profile – Skewness, Kurtosis, Ion Channeling – Implant Damage – Rapid Thermal Annealing.
Unit 3:
Diffusion – Predoposition Diffusion and Drive-in diffusion – Boundary Conditions and Solutions – Diffusion profile as a function of time and temperature – Diffusion Mechanism; Thin Film Deposition – Step Coverage and Aspect Ratio – PVD (Evaporation and Sputtering) process and tools, CVD techniques – LPCVD, PECVD, MOCVD, ALD – Film deposition rate; Epitaxial Growth Techniques – Vapor Phase Epitaxy and Molecular Beam Epitaxy – Structures and Defects in Epitaxial layers – Surface Preparation – Strained Silicon; Contacts and Metallization – RC delay – materials and process for Local and Global Interconnects – Diffusion Barrier – Intermetal Dielectrics – SOI Technology – MOSFET and FinFET process Flows – Sustainability in semiconductor manufacturing.
Objectives and Outcomes
Course Objectives
- Explain the motivation behind device scaling and its implications on power, performance, and process complexity and describe the processes for silicon wafer fabrication starting from sand, including crystal growth.
- Analyze each unit process in VLSI fabrication (such as crystal growth, oxidation, lithography, etching, ion implantation, and deposition), including physical principles, process parameters, and equipment used, and compare them.
- Interpret and model the impact of scaling on fabrication processes such as lithography resolution, doping profiles, deposition of thin films, and interconnect delay
- Design and propose process flows for fabricating MOSFET and FinFET devices.
Course Outcomes: At the end of the course, the student should be able to:
- CO1: Understand the historical evolution and current trends in VLSI scaling, including the impact of Moore’s Law and technology node transitions on circuit performance.
- CO2: Understand the various unit processes, and models involved in the fabrication of semiconductor ICs such as Crystal Growth, Wafer Cleaning, Thermal Oxidation, Thin Film Deposition, Photolithography, Etching, Ion Implantation and Diffusion, and materials used.
- CO3: Analyze the effect of process parameters on device fabrication and analyze the impact of continued scaling on each of the unit processes, and materials to be used.
- CO4: Evaluate the materials, and technology used for Contacts, and Interconnects, and the impact of scaling on back-end processing and CMOS Process Flows
Skills Acquired: Provide an in-depth knowledge on how an IC is fabricated
CO-PO Mapping:
CO/PO |
PO 1 |
PO 2 |
PO 3 |
PSO1 |
PSO2 |
PSO3 |
CO 1 |
3 |
2 |
– |
– |
– |
– |
CO 2 |
3 |
– |
2 |
– |
2 |
– |
CO 3 |
3 |
3 |
2 |
2 |
2 |
– |
CO 4 |
3 |
2 |
3 |
– |
2 |
2 |