Faculty Bio

Year : 2021

Vector Controlled Delay Cell with Nearly Identical Rise/Fall Time for Processor Clock Application

Cite this Research Publication : Dr. Pritam Bhattacharjee, Bidyut K. Bhattacharyya, and Alak Majumder, “Vector Controlled Delay Cell with Nearly Identical Rise/Fall Time for Processor Clock Application”, Journal of Microelectronics, Electronic Components and Materials (SCIE/Scopus), vol. 51, no. 2, p. 112, 2021.

Publisher : Journal of Microelectronics, Electronic Components and Materials (SCIE/Scopus)

Year : 2021

Clock Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC

Cite this Research Publication : Dr. Pritam Bhattacharjee, Prerna Rana, Bidyut K. Bhattacharyya, and Alak Majumder, “Clock Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (Accepted, SCIE/Scopus), 2021.

Publisher : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (Accepted, SCIE/Scopus)

Year : 2020

A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time

Cite this Research Publication : Dr. Pritam Bhattacharjee, Bidyut K. Bhattacharyya, and Alak Majumder, “A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time”, Circuits, Systems, and Signal Processing (SCI/SCIE/Scopus), vol. 40, no. 4, pp. 1569–1588, 2020.

Publisher : Circuits, Systems, and Signal Processing (SCI/SCIE/Scopus), Springer US,

Year : 2019

A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application

Cite this Research Publication : Dr. Pritam Bhattacharjee and Alak Majumder, “A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application”, Journal of Circuits, Systems and Computers (SCIE/Scopus), vol. 28, no. 07, p. 1950108, 2019.

Publisher : Journal of Circuits, Systems and Computers (SCIE/Scopus)

Year : 2019

A variation tolerant data dependent clock gating approach for PSN attenuated low power digital IC

Cite this Research Publication : Dr. Pritam Bhattacharjee, Dhiraj Sarkar, and Alak Majumder, “A variation tolerant data dependent clock gating approach for PSN attenuated low power digital IC”, Ain Shams Engineering Journal (SCIE/Scopus), vol. 10, pp. 573 - 585, 2019.

Publisher : Ain Shams Engineering Journal (SCIE/Scopus)

Year : 2018

Variation aware intuitive clock gating to mitigate on-chip power supply noise

Cite this Research Publication : Alak Majumder and Dr. Pritam Bhattacharjee, “Variation aware intuitive clock gating to mitigate on-chip power supply noise”, International Journal of Electronics (SCI/SCIE/Scopus) , vol. 105, no. 9, pp. 1487-1500, 2018.

Publisher : International Journal of Electronics (SCI/SCIE/Scopus)

Year : 2018

A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chips

Cite this Research Publication : Alak Majumder, Dr. Pritam Bhattacharjee, and Tushar Dhabal Das, “A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chips”, Journal of Circuits, Systems and Computers (SCIE/Scopus), vol. 27, p. 1850146, 2018.

Publisher : Journal of Circuits, Systems and Computers (SCIE/Scopus),

Year : 2017

SPICE modeling for Metal Island Charged Confined Cellular Automata

Cite this Research Publication : Dr. Pritam Bhattacharjee and Kunal Das, “SPICE modeling for Metal Island Charged Confined Cellular Automata”, Journal of Computational and Theoretical Nanoscience (Scopus), vol. 14, pp. 2326-2331, 2017.

Publisher : Journal of Computational and Theoretical Nanoscience (Scopus)

Year : 2017

A 23.52µW / 0.7V Multi-stage Flip-flop Architecture Steered by a LECTOR-based Gated Clock

Cite this Research Publication : Dr. Pritam Bhattacharjee, Alak Majumder, and Bipasha Nath, “A 23.52µW / 0.7V Multi-stage Flip-flop Architecture Steered by a LECTOR-based Gated Clock”, IEIE Transactions on Smart Processing and Computing (Scopus), vol. 6, no. 3, pp. 220-227, 2017.

Publisher : IEIE Transactions on Smart Processing and Computing (Scopus)

Year : 2017

Estimation of Power Dissipation in Ternary Quantum Dot Cellular Automata Cell

Cite this Research Publication : Dr. Pritam Bhattacharjee, Kunal Das, Arijit Dey, Debashis De, and Swarnendu Kumar Chakraborty, “Estimation of Power Dissipation in Ternary Quantum Dot Cellular Automata Cell”, Journal of Low Power Electronics (ESCI/Scopus), vol. 13, no. 2, pp. 231-239, 2017.

Publisher : Journal of Low Power Electronics (ESCI/Scopus), American Scientific Publishers

Year : 2016

Implementation of ternary logic in QCA using SPICE macro-modeling

Cite this Research Publication : Dr. Pritam Bhattacharjee, Arijit Dey, Kunal Das, Swarnendu Kumar Chakraborty, and Rajat Subhra Goswami, “Implementation of ternary logic in QCA using SPICE macro-modeling”, Journal of Engineering Technology (SCIE/Scopus), vol. 5, no. 2, pp. 143-155, 2016.

Publisher : Journal of Engineering Technology (SCIE/Scopus), American Society for Engineering Education,

Year : 2016

SPICE Modeling of LDMOSFET Transistor

Cite this Research Publication : Dr. Pritam Bhattacharjee, “SPICE Modeling of LDMOSFET Transistor”, Journal of Semiconductor Devices and Circuits ISSN: 2455-3379, vol. 3, no. 1, pp. 42-57, 2016.

Publisher : Journal of Semiconductor Devices and Circuits ISSN: 2455-3379, STM Journals

Year : 2014

Methodology of Standard Cell Library Design in .LIB Format

Cite this Research Publication : Arindam Sadhu and Dr. Pritam Bhattacharjee, “Methodology of Standard Cell Library Design in .LIB Format”, Journal of VLSI Design Tool & Technology, vol. 4, no. 1, pp. 30-38, 2014.

Publisher : Journal of VLSI Design Tool & Technology,

Year : 2014

VLSI Transistor and Interconnect Scaling Overview

Cite this Research Publication : Dr. Pritam Bhattacharjee and Arindam Sadhu, “VLSI Transistor and Interconnect Scaling Overview”, Journal of Electronic Design Technology, vol. 5, no. 1, pp. 1–15, 2014.

Publisher : Journal of Electronic Design Technology

Year : 2014

Performance Estimation of VLSI Design

Cite this Research Publication : Arindam Sadhu, Dr. Pritam Bhattacharjee, and Sabnam Koley, “Performance Estimation of VLSI Design”, Journal of VLSI Design Tools and Technology, vol. 4, no. 2, pp. 59–66, 2014.

Publisher : Journal of VLSI Design Tools and Technology

Year : 2021

A QCA based improvised TRNG design for the implementation of secured Nano Communication protocol for ATM services

Cite this Research Publication : Arindam Sadhu, Kunal Das, Debashis De, Maitreyi R. Kanjilal, and Dr. Pritam Bhattacharjee, “A QCA based improvised TRNG design for the implementation of secured Nano Communication protocol for ATM services”, in 3rd International Conference on Computational Advancement in Communication Circuits and Systems (Accepted & Presented, Scopus), 2021.

Publisher : 3rd International Conference on Computational Advancement in Communication Circuits and Systems (Accepted & Presented, Scopus)

Year : 2021

Study of Machine Learning Techniques to Mitigate Fraudulent Transaction in Credit Cards

Cite this Research Publication : Sayan Sikder, Shubhasree Sarkar, Eric G. Varghese, and Dr. Pritam Bhattacharjee, “Study of Machine Learning Techniques to Mitigate Fraudulent Transaction in Credit Cards”, in 3rd International Conference on Machine Intelligence and Signal Processing (Accepted, Scopus), 2021.

Publisher : 3rd International Conference on Machine Intelligence and Signal Processing (Accepted, Scopus)

Year : 2020

A Variable Delay Circuit to Develop Identical Rise/Fall Time in the Output

Cite this Research Publication : Dr. Pritam Bhattacharjee and Alak Majumder, “A Variable Delay Circuit to Develop Identical Rise/Fall Time in the Output”, in Computational Advancement in Communication Circuits and Systems (Scopus), Singapore, 2020, pp. 305–312.

Publisher : Springer Singapore

Year : 2018

Data-Dependent Clock Gating approach for Low Power Sequential System

Cite this Research Publication : Dhiraj Sarkar, Dr. Pritam Bhattacharjee, and Alak Majumder, “Data-Dependent Clock Gating approach for Low Power Sequential System”, in MICRO-2018, Bhubaneswar, India (5th International Conference on Microelectronics, Circuits & Systems), 2018, pp. 49–53.

Publisher : MICRO-2018, Bhubaneswar, India (5th International Conference on Microelectronics, Circuits & Systems)

Year : 2017

Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip

Cite this Research Publication : Alak Majumder and Dr. Pritam Bhattacharjee, “Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip”, in 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) (Scopus), Bhopal, India, 2017, pp. 224–228.

Publisher : 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) (Scopus), IEEE

Year : 2017

LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications

Cite this Research Publication : Dr. Pritam Bhattacharjee, Bipasha Nath, and Alak Majumder, “LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications”, in International Conference on Electronics, Information, and Communication (ICEIC) (Scopus), 2017, pp. 106-109.

Publisher : International Conference on Electronics, Information, and Communication (ICEIC) (Scopus)

Year : 2016

A register-transfer-level description of synthesizable binary multiplier and binary divider

Cite this Research Publication : Dr. Pritam Bhattacharjee, Arindam Sadhu, and Kunal Das, “A register-transfer-level description of synthesizable binary multiplier and binary divider”, in 2016 International Conference on Microelectronics, Computing and Communications (MicroCom) (Scopus), Durgapur, India, 2016, pp. 1–6.

Publisher : 2016 International Conference on Microelectronics, Computing and Communications (MicroCom) (Scopus), IEEE

Year : 2016

LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder

Cite this Research Publication : Dr. Pritam Bhattacharjee and Alak Majumder, “LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder”, in 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) (Scopus), Gwalior, India, 2016, pp. 250–254.

Publisher : 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) (Scopus), IEEE

Year : 2016

A 90 nm leakage control transistor based clock gating for low power flip flop applications

Cite this Research Publication : Dr. Pritam Bhattacharjee, Alak Majumder, and Tushar Dhabal Das, “A 90 nm leakage control transistor based clock gating for low power flip flop applications”, in 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS) (Scopus), Abu Dhabi, United Arab Emirates, 2016, pp. 1–4.

Publisher : 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS) (Scopus), IEEE

Year : 2015

SPICE Modeling and Analysis for Metal Island Ternary QCA Logic Device

Cite this Research Publication : Dr. Pritam Bhattacharjee, Kunal Das, Mallika De, and Debashis De, “SPICE Modeling and Analysis for Metal Island Ternary QCA Logic Device”, in Information Systems Design and Intelligent Applications (Scopus), New Delhi, 2015, pp. 33–41.

Publisher : Information Systems Design and Intelligent Applications (Scopus), Springer India,

Year : 2014

Characterization of Ternary Quantum dot cellular Automata for III-V Materials

Cite this Research Publication : Dr. Pritam Bhattacharjee, Arijit Dey, Das, K., Mallika De, and Debashis De, “Characterization of Ternary Quantum dot cellular Automata for III-V Materials”, in National Conference on Nanoscience and Nanotechnology (NS&NT-2014), 2014.

Publisher : National Conference on Nanoscience and Nanotechnology (NS&NT-2014)

Year : 2019

Understanding of On-Chip Power Supply Noise: Suppression Methodologies and Challenges

Cite this Research Publication : Dr. Pritam Bhattacharjee, Prerna Rana, and Alak Majumder, “Understanding of On-Chip Power Supply Noise: Suppression Methodologies and Challenges”, in Recent Trends in Communication Networks, IntechOpen, (WoS/Book SCI), United Kingdom: IntechOpen Limited, 2019.

Publisher : Recent Trends in Communication Networks, IntechOpen, (WoS/Book SCI),

Year : 2017

Voltage Keeper Based Robust Flip Flop For Low Power Applications, Indian Patent File Application No. (Kolkata, India): 201731044358

Cite this Research Publication : Alak Majumder, Dr. Pritam Bhattacharjee, and Bipasha Nath, “Voltage Keeper Based Robust Flip Flop For Low Power Applications, Indian Patent File Application No. (Kolkata, India): 201731044358”, 2017.

Publisher : Kolkata, India (2017)

Year : 2017

Voltage Keeper Based Robust Flip Flop For Low Power Applications

Cite this Research Publication : Alak Majumder, Dr. Pritam Bhattacharjee, and Bipasha Nath, “Voltage Keeper Based Robust Flip Flop For Low Power Applications, Indian Patent File Application No. (Kolkata, India): 201731044358”, 2017.