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Variation aware intuitive clock gating to mitigate on-chip power supply noise

Publication Type : Journal Article

Publisher : International Journal of Electronics (SCI/SCIE/Scopus)

Source : International Journal of Electronics (SCI/SCIE/Scopus) , Taylor & Francis, Volume 105, Issue 9, p.1487-1500 (2018)

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Keywords : Average di/dt, Clock gating, LCT, Power Supply Noise, Static and Dynamic Power Dissipation

Campus : Amritapuri

School : Department of Computer Science and Engineering, School of Engineering

Department : Computer Science and Engineering, Computer Science

Year : 2018

Abstract : ABSTRACTWith the advent of semiconductor process technology, both the dynamic and static power consumption have become major concerns for the circuit designers. Though clock gating (CG) is a potentially accomplished technique to minimise the dynamic power, it generally fails to cut down the static power dissipation. To address the same, we have unveiled a new CG scheme incorporating leakage control transistor, which simultaneously curbs the static and dynamic power along with the alleviation of power supply noise (PSN) in silicon chips by smartly controlling the current ramp (di/dt) and average current i(t): the main contributors to PSN. The proposed CG does not only save average, dynamic and static power by 84.34%, 90.33% and 66.73%, respectively, but also reduces PSN by 84.44% with respect to its non-gated counterpart when simulated using Cadence Virtuoso® for 90 nm Generic Process Design Kit at a switching frequency of 5 GHz and power supply voltage of 1.1 V.

Cite this Research Publication : Alak Majumder and Dr. Pritam Bhattacharjee, “Variation aware intuitive clock gating to mitigate on-chip power supply noise”, International Journal of Electronics (SCI/SCIE/Scopus) , vol. 105, no. 9, pp. 1487-1500, 2018.

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