Publication Type : Journal Article
Publisher : Journal of Circuits, Systems and Computers (SCIE/Scopus),
Source : Journal of Circuits, Systems and Computers (SCIE/Scopus), Volume 27, Number 09, p.1850146 (2018)
Url : https://doi.org/10.1142/S0218126618501463
Keywords : Clock gating, LECTOR and Average Power Dissipation, Power and Ground Noise
Campus : Amritapuri
School : Department of Computer Science and Engineering, School of Engineering
Center : Electronics Communication and Instrumentation Forum (ECIF)
Department : Computer Science and Engineering, Computer Science
Year : 2018
Abstract : As the performing ability of a silicon chip relies on the power supply voltage, it must be configured using genuine power and ground bond pads for mitigating power and ground noise (PGN), which is directly boosted by the increasing peaks of instantaneous current i(t) and current ramp (di/dt). To address the same, a novel and compact clock gating (CG) scheme is unveiled in this paper to effectively control the peak of i(t) and di/dt, thereby subduing PGN. The new CG arrangement is simulated for 90nm Predictive Technology Model (PTM90), where it is observed that the scheme reduces 88.80% of i(t) and 84.19% of average di/dt in comparison to its no gating counterpart along with a reduction of 80.14% in average power dissipation. These results are found to be more prominent when the proposed circuit configuration is tested in 90nm Generic Process Design Kit (GPDK90), proclaiming 88.75% and 84.34% reduction in average di/dt and average power, respectively, to illustrate its capability of truncating PGN in silicon chips.
Cite this Research Publication : Alak Majumder, Dr. Pritam Bhattacharjee, and Tushar Dhabal Das, “A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chips”, Journal of Circuits, Systems and Computers (SCIE/Scopus), vol. 27, p. 1850146, 2018.