Publication Type : Conference Paper
Publisher : 2016 International Conference on Microelectronics, Computing and Communications (MicroCom) (Scopus), IEEE
Source : 2016 International Conference on Microelectronics, Computing and Communications (MicroCom) (Scopus), IEEE, Durgapur, India, p.1–6 (2016)
Url : https://ieeexplore.ieee.org/abstract/document/7522470
Keywords : back-end, binary divider, Clocks, Computers, dividing circuits, front-end, hardware description language, hardware description languages, Hardware design languages, Microprocessor, Microprocessor chips, Microprocessors, multiplying circuits, register transfer level description, registers, RTL, Synchronization, synthesizable binary multiplier, synthesizable multiplier and divider, very high specific integrated circuit, Very large scale integration, VHDL
Campus : Amritapuri
School : Department of Computer Science and Engineering, School of Engineering
Department : Computer Science
Year : 2016
Abstract : The paper depicts the RTL (Register Transfer Level) description of Binary Multiplier and Binary Divider. The descriptions are synchronized to the operating clock of the microprocessor. The major operations that get a highlight in this paper is that the multiplier and divider are synthesizable. VHDL (Very High Specific Integrated Circuit - Hardware Description Language) is the language of construct for the design. This work focuses to show that synchronized applications can be implemented at the front-end level of VLSI design methodology.
Cite this Research Publication : Dr. Pritam Bhattacharjee, Arindam Sadhu, and Kunal Das, “A register-transfer-level description of synthesizable binary multiplier and binary divider”, in 2016 International Conference on Microelectronics, Computing and Communications (MicroCom) (Scopus), Durgapur, India, 2016, pp. 1–6.