Course

Unit 1:

Introduction to Physical IC Design–Objectives–VLSI Physical Design Cycle – CMOS circuit and layout design –Partitioning algorithms–Floor Planning algorithms– Specific Floor Planning Problems – Pin assignment.

Unit 2:

Placement: Constraints and algorithm – Timing Analysis: Clock Design – Clock Distribution Networks – Clock Tree Synthesis – Clock Power Analysis – Routing methodology: Grid Routing- Global Routing – Detail Routing – Channel Routing Problem.

Unit 3:

Analysis and Optimization Types–Best/Worst Analysis –Parasitic Extraction (RC Extraction)– Resistance extraction, Capacitance extraction, Inductance and impedance (RLC) extraction-
Final Validation– Net List Output–GDS2 Output.

Course Objectives

• To acquire knowledge of Physical design of simple logic gates using CMOS transistors.
• To provide knowledge involved in Partitioning, floorplanning, placement, clock tree synthesis, routing, and extraction of layout.
• To provide knowledge on the EDA tools used for Back end design of ICs.

Course Outcomes: At the end of the course, the student should be able to

• CO1: Understand the back end flow of VLSI design cycle.
• CO2: Apply techniques for ASIC design flow using standard cell libraries.
• CO3: Apply the simple optimization techniques in the back end ASIC design flow.
• CO4: Analyze and comprehend the physical design flow and related design, synthesis, test and timing issues.

Skills Acquired: Provide a practical approach for design of Application Specific
Integrated Circuits, using Synopsys/Cadence EDA tool flow.

CO-PO Mapping:

1. “Digital ASIC Design, A Tutorial on the Design Flow”, Digital ASIC Group, October 20, 2005, Lund University.
2. Majid Sarrafzadeh, C. K. Wong , “An introduction to VLSI physical design”, McGraw Hill, 1996, ISBN 0070571945, 9780070571945, 334 pages
3. Khosrow Golshan, “Physical design essentials: an ASIC design implementation perspective”, Springer, 2007, ISBN 0387366423, 9780387366425, 211 pages
4. Ban P. Wong, Anurag Mittal, Yu Cao, Greg Starr Contributor Ban P. Wong, Anurag Mittal, Yu Cao, “Nano- CMOS circuit and physical design”, John Wiley and Sons, 2004.
5. Andrew B. Kahng, Jens Lienig, Igor L. Markov, From Graph Partitioning to Timing Closure, Jin Hu, Springer 2011.
6. K. Golshan, Physical Design Essentials: An ASIC Design Implementation Perspective, Springer, 2010.