Year : 2022
Design of a Programmable Low Power Linear Feedback Shift Register for BIST Applications
Cite this Research Publication : M. B, G. Remadevi and R. Bakthavatchalu, "Design of a Programmable Low Power Linear Feedback Shift Register for BIST Applications," 2022 IEEE International Test Conference India (ITC India), 2022, pp. 1-4, doi: 10.1109/ITCIndia202255192.2022.9854556
Publisher : IEEE
Year : 2022
Design and Analysis of Multi-Bit Linear Feedback Shift Register based PRNG with FPGA Implementation using different Primitive Polynomials
Cite this Research Publication : S. Sony, A. P. V and G. R.S., "Design and Analysis of Multi-Bit Linear Feedback Shift Register based PRNG with FPGA Implementation using different Primitive Polynomials," 2022 2nd International Conference on Intelligent Technologies (CONIT), 2022, pp. 1-7, doi: 10.1109/CONIT55038.2022.9848174
Publisher : IEEE
Year : 2022
Reconfigurable Linear Feedback Shift Register
Cite this Research Publication : Madhulatha Kamma , Jyothika Karasani , Somanathan, Geethu Remadevi , Bhakthavathchalu, Ramesh ,"Reconfigurable Linear Feedback Shift Register",https://www.scopus.com/record/display.uri?eid=2-s2.0-85127327122&origin=resultslist&sort=plf-f
Publisher : Elsevier
Year : 2022
Reconfigurable and Parameterizable Pseudorandom Pattern Generators for Built-in Self Test
Cite this Research Publication : Madhulatha, Kamma, Jyothika, Karasani,Harini, Sirikonda Venkata Bala, Somanathan, Geethu Remadevi, Bhakthavathchalu, Ramesh ," Reconfigurable and Parameterizable Pseudorandom Pattern Generators for Built-in Self Test",7th International Conference on Communication and Electronics Systems, ICCES 2022 - Proceedings
Publisher : Elsevier
Year : 2022
A Proposal for Programmable Pattern Generator and its FPGA implementation
Cite this Research Publication : Bhakthavatchalu Ramesh, Somanathan Geethu Remadevi,"A Proposal for Programmable Pattern Generator and its FPGA implementation", 3rd IEEE International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI SATA 2022
Publisher : Elsevier
Year : 2022
A Proposal for Low Power Test Pattern Generator
Cite this Research Publication : Maddala Vamsi Krishna, Duppala Tagore, Mani Srikara Yaswanth Nandigam, Palla Narasimha, Udayagiri Rahul and Geethu R. S., "A Proposal for Low Power Test Pattern Generator," 2022 4th International Conference on Smart Systems and Inventive Technology (ICSSIT), 2022, pp. 648-653, doi: 10.1109/ICSSIT53264.2022.9716394.
Publisher : IEEE
Year : 2022
A Programmable and Parameterisable Reseeding Linear Feedback Shift Register
Cite this Research Publication : Hudhaifah Ibn Saleem; Geethu R. S. and Ramesh Bhakthavatchalu, "A Programmable and Parameterisable Reseeding Linear Feedback Shift Register," 2022 Second International Conference on Artificial Intelligence and Smart Energy (ICAIS), 2022, pp. 1629-1633, doi: 10.1109/ICAIS53314.2022.9742870.
Publisher : IEEE
Year : 2022
A Proposal for Design and Implementation of a Low Power Test Pattern Generator for BIST Applications
Cite this Research Publication : Malini Mukherjee, Geethu R S and Ramesh Bhakthavatchalu, "A Proposal for Design and Implementation of a Low Power Test Pattern Generator for BIST Applications," 2022 Second International Conference on Artificial Intelligence and Smart Energy (ICAIS), 2022, pp. 1520-1524, doi: 10.1109/ICAIS53314.2022.9742920.
Publisher : IEEE
Year : 2022
Design and Implementation of Programmable Multiple Input Signature Register
Cite this Research Publication : Ashutosh Agnihotri; Geethu Remadevi Somanathan; Ramesh Bhakthavatchalu, "Design and Implementation of Programmable Multiple Input Signature Register," 2022 Second International Conference on Artificial Intelligence and Smart Energy (ICAIS), 2022, pp. 1536-1540, doi: 10.1109/ICAIS53314.2022.9742968.
Publisher : IEEE
Year : 2022
Programmable Variable-Length Pseudo-Random Sequence Generator
Cite this Research Publication : Doriginti Mohammad, Kanna Rakesh, Geethu Remadevi Somanathan and Ramesh Bhakthavatchalu, "Programmable Variable-Length Pseudo-Random Sequence Generator," 2022 Second International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT), 2022, pp. 1-4, doi: 10.1109/ICAECT54875.2022.9808067.
Year : 2021
Analysis of a Novel Reseeding Pattern Generator
Cite this Research Publication : Vikranth, Chinnapapakkagari Sreenivasa, Mohammad, Doriginti, Somanathan, Geethu Remadevi, Bhakthavatchalu, Ramesh," Analysis of a Novel Reseeding Pattern Generator",Proceedings - 2nd International Conference on Smart Electronics and Communication, ICOSEC 2021
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Publisher : Elsevier
Year : 2021
Design and Analysis of Test Pattern Generator by combining internal and external LFSR
Cite this Research Publication : Vikranth, Chinnapapakkagari Sreenivasa, Rakesh, Kanna, Jagadeesh, Bodavula, Mohammad, Doriginti, Somanathan, Geethu Remadevi, Bhakthavatchalu, Ramesh, "Design and Analysis of Test Pattern Generator by combining internal and external LFSR", Proceedings of the 5th International Conference on Trends in Electronics and Informatics, ICOEI 2021.
Publisher : Elsevier
Year : 2021
Design and analysis of gray code generator as test pattern generator
Cite this Research Publication : Narasimha, Palla, Krishna, Maddala Vamsi , Somanathan, Geethu Remadevi,Bhakthavatchalu, Ramesh," Design and analysis of gray code generator as test pattern generator", Proceedings of the 6th International Conference on Communication and Electronics Systems, ICCES 2021
Publisher : Elsevier
Year : 2021
Logic Obfuscation Technique for Securing Test Pattern Generators
Cite this Research Publication : Bhakthavatchalu Ramesh ,Sumanth, B. Naga, Naidu P. Shanmukha Naga, Koduri, Pavan Sri Ram, v, Somanathan, Geethu Remadevi,"Logic Obfuscation Technique for Securing Test Pattern Generators",https://www.scopus.com/record/display.uri?eid=2-s2.0-85116708198&origin=resultslist&sort=plf-f
Publisher : Elsevier
Year : 2021
Balanced Scan Chain Analysis to Improve Fault Coverage in VLSI circuits
Cite this Research Publication : R.S. Geethu, Bhakthavathchalu, R., and Krishnakumar, M., “Balanced Scan Chain Analysis to Improve Fault Coverage in VLSI circuits”, in 2021 6th International Conference on Inventive Computation Technologies (ICICT), Coimbatore, India, 2021.
Publisher : 2021 6th International Conference on Inventive Computation Technologies (ICICT),
Year : 2021
Secured Test Pattern Generators for BIST
Cite this Research Publication : S. Naga Naidu P., B., N. Sumanth, Pavan, S. Ram Koduri, M., S. Ram Teja, R.S. Geethu, and Bhakthavatchalu, R., “Secured Test Pattern Generators for BIST”, in 2021 5th International Conference on Computing Methodologies and Communication (ICCMC), Erode, India, 2021.
Publisher : 2021 5th International Conference on Computing Methodologies and Communication (ICCMC)
Year : 2020
Synthesis of Synchronous Gray Code Counters by Combining Mentor Graphics HDL Designer and Xilinx VIVADO FPGA Flow
Cite this Research Publication : S. Satya Sri Seeram, Polireddi, S. Naga Naidu, R.S. Geethu, and Bhakthavatchalu, R., “Synthesis of Synchronous Gray Code Counters by Combining Mentor Graphics HDL Designer and Xilinx VIVADO FPGA Flow”, in 2020 International Conference on Communication and Signal Processing (ICCSP), Chennai, India, 2020.
Publisher : 2020 International Conference on Communication and Signal Processing (ICCSP),
Year : 2020
A Proposal for Synthesis of Synchronous Counters
Cite this Research Publication : N. B. Sumanth, B. Reddy, L., R.S. Geethu, and , “A Proposal for Synthesis of Synchronous Counters”, in 2020 4th International Conference on Trends in Electronics and Informatics (ICOEI)(48184), Tirunelveli, India, 2020.
Publisher : 2020 4th International Conference on Trends in Electronics and Informatics (ICOEI)(48184),
Year : 2020
Synthesis of Pseudorandom Number Generator by Combining Mentor Graphics HDL Designer and Xilinx Vivado FPGA Flow
Cite this Research Publication : R.S. Geethu, Bhakthavathchalu, R., and Krishnakumar, M., “Synthesis of Pseudorandom Number Generator by Combining Mentor Graphics HDL Designer and Xilinx Vivado FPGA Flow”, in Advances in Communication Systems and Networks, Singapore, 2020.
Publisher : Advances in Communication Systems and Networks,
Year : 2019
Comparative Study of Test Pattern Generation Systems to Reduce Test Application Time
Cite this Research Publication : P. Snehal Dilip, R.S. Geethu, and Bhakthavatchalu, R., “Comparative Study of Test Pattern Generation Systems to Reduce Test Application Time”, in 2019 9th International Symposium on Embedded Computing and System Design (ISED), Kollam, India, 2019.
Publisher : 2019 9th International Symposium on Embedded Computing and System Design (ISED),
Year : 2019
Reseeding LFSR for Test Pattern Generation
Cite this Research Publication : P. Snehal Dilip, R.S. Geethu, and Bhakthavatchalu, R., “Reseeding LFSR for Test Pattern Generation”, in 2019 International Conference on Communication and Signal Processing (ICCSP), Chennai, India, 2019.
Publisher : 2019 International Conference on Communication and Signal Processing (ICCSP),
Year : 2018
Architecture of Parallel CRC Encoder Using State Space Transformations
Cite this Research Publication : L. S. Prabha and R.S. Geethu, “Architecture of Parallel CRC Encoder Using State Space Transformations”, in 2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Bengaluru, India, 2018.
Publisher : 2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT),
Year : 2018
Design for a Programmable Alarm Clock using Alphanumeric Display (PACAD)
Cite this Research Publication : K. Sai Sandilya, Eswari, M., R.S. Geethu, B, B., and , “Design for a Programmable Alarm Clock using Alphanumeric Display (PACAD)”, in 2018 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), Madurai, India, 2018.
Publisher : 2018 IEEE International Conference on Computational Intelligence and Computing Research
Year : 2015
A proposal for source separation of ground borne vibration signals and its FPGA implementation
Cite this Research Publication :
R.S. Geethu, Kumar, MbKrishna, and George, S. Nc, “A proposal for source separation of ground borne vibration signals and its FPGA implementation”, in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, 2015
Publisher : 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015
Year : 2014
A scheme for source separation of ground borne vibrations
Cite this Research Publication : K. M. Kumar, R.S. Geethu, and Pramod, K. V., “A scheme for source separation of ground borne vibrations”, in International Conference on Communication and Network Technologies, Sivakasi, India, 2014.
Publisher : International Conference on Communication and Network Technologies,
Year : 2014
Source Separation of ground borne low level vibration signals using statistical methods
Cite this Research Publication : K. Kumar M., R.S. Geethu, and V., P. K., “Source Separation of ground borne low level vibration signals using statistical methods”, in International Conference on Advances in Computing, Communication and Information Science (ACCIS-2014), 2014.
Publisher : International Conference on Advances in Computing, Communication and Information Science.
Year : 2012
A Proposal for Source Separation of Heartbeat Sounds and Its FPGA Implementation
Cite this Research Publication : R.S. Geethu, George, S. N., and M. Kumar, K., “A Proposal for Source Separation of Heartbeat Sounds and Its FPGA Implementation”, in 2012 International Conference on Communication Systems and Network Technologies, Rajkot, Gujarat, India, 2012.
Publisher : IEEE
Year : 2010
A Life Tracking System based on Audio Source Separation
Cite this Research Publication : K. Kumar M, V, P. K., and R.S. Geethu, “A Life Tracking System based on Audio Source Separation”, in IETE Zonal seminar on Networking Paradigms and Cyber Security, 2010.
Publisher : IETE Zonal seminar on Networking Paradigms and Cyber Security,