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Publication Type : Conference Paper
Publisher : 2020 International Conference on Communication and Signal Processing (ICCSP),
Source : 2020 International Conference on Communication and Signal Processing (ICCSP), IEEE, Chennai, India (2020)
Campus : Amritapuri
School : School of Engineering
Department : Electronics and Communication
Year : 2020
Abstract : Increased complexity of circuits builds more challenge for testing the functionality as well as errors in the circuit. One of the challenges in testing is increased power requirements during test mode. This paper proposes a scheme for test pattern generation based on gray code. A new approach of combining Mentor Graphics HDL Design and Xilinx VIVADO is used for generating the proposed test pattern generator. Parameters like area, power are analyzed and compared with the corresponding gate level models.
Cite this Research Publication : S. Satya Sri Seeram, Polireddi, S. Naga Naidu, R.S. Geethu, and Bhakthavatchalu, R., “Synthesis of Synchronous Gray Code Counters by Combining Mentor Graphics HDL Designer and Xilinx VIVADO FPGA Flow”, in 2020 International Conference on Communication and Signal Processing (ICCSP), Chennai, India, 2020.