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Publication Type : Conference Paper
Publisher : 2019 9th International Symposium on Embedded Computing and System Design (ISED),
Source : 2019 9th International Symposium on Embedded Computing and System Design (ISED), IEEE, Kollam, India (2019)
Campus : Amritapuri
School : School of Engineering
Department : Electronics and Communication
Year : 2019
Abstract : According to the Moore's Law, density of the circuit is increasing which results difficulty in testing the circuit. Resource utilization, time required to test the circuit, power required to test the circuit are some of the parameters which affects testing. Test application time is much high because of the use of scan-in and scan-out chains. This paper proposes a gray code counter which can be used as random test pattern generator. The proposed method is compared with reseeding LFSR technique to analyze the performance of the pseudorandom test pattern generation. Fault and fault free circuits can be detected by applying test patterns generated from the proposed system to ISCAS'89 benchmark circuit. Hamming distance is used to detect the bit changes with respect to position of the bits. Reducing the number of bit changes in consecutive test patterns will affect the test time which also helps to decrease the memory requirement. The proposed method generates the sequence which has a hamming distance 1. The circuit can also be integrated in BIST for more rebate results.
Cite this Research Publication : P. Snehal Dilip, R.S. Geethu, and Bhakthavatchalu, R., “Comparative Study of Test Pattern Generation Systems to Reduce Test Application Time”, in 2019 9th International Symposium on Embedded Computing and System Design (ISED), Kollam, India, 2019.