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Publication Type : Conference Paper
Publisher : 2021 6th International Conference on Inventive Computation Technologies (ICICT),
Source : 2021 6th International Conference on Inventive Computation Technologies (ICICT), IEEE, Coimbatore, India (2021)
Campus : Amritapuri
School : School of Engineering
Department : Electronics and Communication
Year : 2021
Abstract : Built-in-Self-Test allows a circuit to test itself, and finds more use with standalone and mission critical applications like medical or automotive. Testability of a circuit is a key factor which determines the level of testing that can be done to find faults in the circuit. Scan chains can be used in circuits with flip-flops to enhance the testability. Effectiveness of scan designs largely depends on the quantity of flip-flops and length, number of scan chains. This paper analyses the circuits with full scan designs using the cases of maximum number and minimum number of equal length scan chains in all circuits. The number of PI/PO, total faults, fault coverage, CPU time, test inputs required are compared. The experiments are done on IS CAS'89 benchmarked circuits.
Cite this Research Publication : R.S. Geethu, Bhakthavathchalu, R., and Krishnakumar, M., “Balanced Scan Chain Analysis to Improve Fault Coverage in VLSI circuits”, in 2021 6th International Conference on Inventive Computation Technologies (ICICT), Coimbatore, India, 2021.