Qualification: 
M.Tech, BE
remya@am.amrita.edu

Remya currently serves as Vice Chairperson and Assistant Professor at the Department of Electronics and Communication Engineering, School of Engineering, Amrita Vishwa Vidyapeetham, Amritapuri. She completed her MTech in VLSI Design. Current research area include Biomedical Image Analysis using Computer Vision Algorithms.

Publications

Publication Type: Conference Paper

Year of Publication Title

2020

P. Parvathy and Remya Ajai A. S., “VLSI Implementation of Blowfish Algorithm for Secure Image Data Transmission”, in 2020 International Conference on Communication and Signal Processing (ICCSP), Chennai, India, 2020.[Abstract]


Nowadays, almost every person in the world uses the Internet to communicate to each other. For various applications, different types of images are transmitted over the Internet. Such photos normally contain either private or confidential data. Ensuring the confidentiality, honesty, authentication and nonrepudiation of images during transmission is therefore a prerequisite for image transmission. Blowfish is an open source algorithm thus making it available for anyone to use this algorithm for their desired purpose. Because of the fewer number of rounds and the operations used in the rounds being less complex, blowfish is considered relatively a fast block cipher after the key schedule has been completed. In this project, implementation of blowfish algorithm is done in MATLAB version 2019a. Verilog implementation is also done.

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2020

Remya Ajai A. S. and Gopalan, S., “Analysis of Active Contours Without Edge-Based Segmentation Technique for Brain Tumor Classification Using SVM and KNN Classifiers”, in Advances in Communication Systems and Networks, Singapore, 2020.[Abstract]


Classification of brain tumors using machine learning technology in this era is very relevant for the radiologist to confirm the analysis more accurately and quickly. The challenge lies in identifying the best suitable segmentation and classification algorithm. Active contouring segmentation without edge algorithm can be preferred due to its ability to detect shapeless tumor growth. But the perfectness of segmentation is influenced by the image enhancement techniques that we apply on raw MRI image data. In this work, we analyze different pre-processing algorithms that can be applied for image enhancement before performing the active contour without edge-based segmentation. The accuracy is compared for both linear kernel SVM and KNN classifiers. High accuracy is achieved when image sharpening or contrast stretching algorithm is used for image enhancement. We also analyzed that KNN is more suitable for brain tumor classification than linear SVM when active contouring without edge method of segmentation technique is used. MATLAB R2017b is used as the simulation tool for our analysis.

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2019

S. SasankVarthakavi, Babu, D. Rohith Pra, Reddy, L. Kumar Redd, and Remya Ajai A. S., “Analysis of preprocessing algorithms for face detection using KNN and SVM classifiers”, in 10th International Conference on Advances in Computing, Control, and Telecommunication Technologies, ACT 2019, 2019.

2019

J. N. Reddy, Vinod, K., and Remya Ajai A. S., “Analysis of Classification Algorithms for Plant Leaf Disease Detection”, in 2019 IEEE International Conference on Electrical, Computer and Communication Technologies (ICECCT), Coimbatore, India, 2019.[Abstract]


Agribusiness is the essential occupation in India, that assumes a vital job in the economy of the nation. Yearly 15.7 percentage of the crops are being lost due to attack by insect pests and diseases [1]. The diseases caused will lead to a reduction of quality and quantity of crops. To maintain the health of the plant, it is required to identify the infection and give reasonable consideration. It is difficult to do physically because the human eye cannot observe the minute variations of the infected part of the leaf. In this way, we have built up a framework programming utilizing Matlab [2] to distinguish plant leaf illnesses by utilizing picture handling procedures. The software is produced so that a man even who don't have earlier learning about the plants, and their ailments can effectively recognize infected leaves. We have utilized k-means clustering to distinguish the tainted region of the plant leaf. The diseased recognition part incorporates picture obtaining, image pre-processing, segmentation and feature extraction and SVM classification.

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2019

J. Harikrishnan, Sudarsan, A., Sadashiv, A., and Remya Ajai A. S., “Vision-Face Recognition Attendance Monitoring System for Surveillance using Deep Learning Technology and Computer Vision”, in 2019 International Conference on Vision Towards Emerging Trends in Communication and Networking (ViTECoN), Vellore, India, 2019.[Abstract]


Nowadays, Artificial Neural networks can be trained over several billion images and can be used to detect and recognize faces with relative ease and flexibility in an instant. This concept is used in the implementation of this real time attendance cum surveillance system that can be prototyped and set into action. Some of the major applications of this innovative method include face attendance using a single snap mode in smartphones for university classes, further real-time facial recognition surveillance of lab facilities and work places which can set this as a first line of defense against intruders from gaining access. The user-friendly graphical user interface provides flexibility and ease in running these powerful face recognition algorithms powered by deep-learning. We have achieved a maximum recognition accuracy of 74 percent while running the real time surveillance algorithm. This work was done as a solution to the absence of a robust and user friendly face recognition attendance system.

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2019

V. S. Aparna, Rajan, A., Jairaj, I., Nandita, B., Madhusoodanan, P., and Remya Ajai A. S., “Implementation of AES Algorithm on Text And Image using MATLAB”, in 2019 3rd International Conference on Trends in Electronics and Informatics (ICOEI), Tirunelveli, India, 2019.[Abstract]


One of the major problems faced by the world today is Data Security. In reality communication channel which is used to transfer data from transmitter to receiver is highly insecure. To resolve this problem the data is being manipulated to another form, so that the person with access to the secret key can only read it. This process of manipulation of original data to another form so that eavesdropper cannot access it, is known as encryption. Advanced Encryption Standard (AES) is the most commonly used algorithm for data encryption. This algorithm can be applied on both text and image. In this paper the input to AES algorithm is Text and an image, which results in encrypted output. This encrypted output is given as an input to AES decryption algorithm, which results in decrypted output. The algorithm is implemented using MATLAB software.

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2019

T. Bhagya, Anand, K., Kanchana, D. S., and Remya Ajai A. S., “Analysis of Image Segmentation Algorithms for the Effective Detection of Leukemic Cells”, in 2019 3rd International Conference on Trends in Electronics and Informatics (ICOEI), Tirunelveli, India, 2019.[Abstract]


Image segmentation plays a vital role in medical image processing. Different pre-processing methods yield different results. The pre-processing methods such as histogram stretching with erosion and dilation, average filter and median filter along with histogram stretching is applied to the four different segmentation algorithms which are Otsu's thresholding, Watershed based segmentation, Canny edge detection and K-mean clustering. These algorithms are used to segment Acute Lymphoblastic Leukemia datasets and the parameters such as precision, accuracy and sensitivity of the results are calculated so as to find a better algorithm which is suitable for segmentation of the leukemic cells.

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2019

S. Krishna and Remya Ajai A. S., “Analysis of Three Point Checklist and ABCD Methods for the Feature Extraction of Dermoscopic Images to Detect Melanoma”, in 2019 9th International Symposium on Embedded Computing and System Design (ISED), Kollam, India, 2019.[Abstract]


A man's danger of causing malignancy depends upon numerous components such as age, hereditary qualities, risk to chance variables. There has been a progressive increase in the occurrence of skin cancers over the last few decades. So, a Computer Aided Diagnostic (CAD) system is highly in demand to assist doctors to reduce their physical effort for the melanoma detection. This work aims to develop efficient feature extraction algorithms for classification of melanoma and non-melanoma cases to develop a CAD system. The algorithms are verified via images available in the PH 2 dataset. The ABCD and 3 point checklist features are extracted from the preprocessed images. These features are analysed and compared using various classification algorithms such as Sequential Minimal Optimisation (SMO), Logistic regression, Random Forest, J48 decision tree available in WEKA software. In the analysis, it is found that 3 - Point checklist has a better accuracy and precision compared to ABCD method for various classifiers tested in Weka 3.8.2 software.

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2018

J. Amrutha and Remya Ajai A. S., “Performance analysis of Backpropagation Algorithm of Artificial Neural Networks in Verilog”, in 2018 3rd IEEE International Conference on Recent Trends in Electronics, Information Communication Technology (RTEICT), Bangalore, India, 2018.[Abstract]


Artificial neural networks learn or get trained to execute definite tasks, instead of programmed computational systems through training algorithms such as Backpropagation algorithm. It is the basic tool for pattern classification application of ANN in field of medical diagnosis and remote sensing. This method involves changing the weights in the network using a training set of input output examples. Digital implementation of these neural networks for classification is suitable as it preserves the parallel architecture of the neurons and can be reconfigured by the user with FPGA. This parallelism in neural networks make it potentially fast for computation of tasks. This work implements backpropagation training algorithm in verilog with Modelsim-Altera 6.5b for a feedforward neural network. Since multiplier algorithms determine the operational speed and power consumption; a performance analysis is made based on different multipliers. The work can be further extended to the implementation of artificial neural networks on FPGA and to implement a classification application in the trained network.

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2016

A. Suresh and Remya Ajai A. S., “VLSI implementation of text to image encryption algorithm based on private key encryption”, in 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), Chennai, India, 2016.[Abstract]


In cryptographic applications, the data sent to a remote host are encrypted at the source machine using an encryption key and then the encrypted data are sent to the destination machine, where it is decrypted to get the original data. Thus the attacker will not have the encryption key which is required to get the original data and so a hacker can do nothing with any cryptographic system. Reprogrammable devices such as Field Programmable Gate Arrays (FPGAs) are used for hardware implementations of cryptographic algorithms. As FPGA devices progressed both in terms of resources and performance, the latest FPGAs provide solutions that are easily customizable for system connectivity, DSP, and data processing applications. In this paper, implementation of an efficient cryptographic algorithm is done in Xilinx SPARTEN 3E FPGA. Also the algorithm is analyzed by calculating the number of all possible key permutations.

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2016

S. Ammu and Remya Ajai A. S., “VLSI implementation of Boolean algebra based cryptographic algorithm”, in 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), Chennai, India, 2016.[Abstract]


FPGA is an integrated circuit, which can be reconfigured by designers themselves. FPGA are reprogrammable silicon chips. Field Programmable Gate Arrays (FPGA) are used for hardware implementations of cryptographic algorithm. This paper presents an FPGA based Hardware implementation of Boolean algebra based cryptographic algorithm for secure transmission. Using this algorithm, we can hide the meaning of a message in unreadable characters. ASCII values of characters, numbers and symbols are used for encryption and decryption. ASCII values converted into binary number and it takes 32 bits in implementation. Boolean operations such as 1's and 2's complement and xor operation are used for encryption and decryption. Xilinx - sparton3E FPGA kit is used for the synthesizing and implementation of cryptographic algorithm.

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2012

Ka Praveen, Poornachandran, Pb, and Remya Ajai A. S., “Implementation of DES using pipelining concept with skew core key scheduling in secure transmission of images”, in ACM International Conference Proceeding Series, Coimbatore, 2012, pp. 637-641.[Abstract]


Digital image processing is a very expanding area with applications reaching out into various fields such as defence, medicine, space exploration, authentication, automated industry inspection and many more areas. Many digital communication systems require reliable security in processing and transmission of digital images. The fast development of internet in the digital world demands more concern in to the security of digital images and have attracted much attention [1]. Encryption of digital images is the preferred way while transmission and can be used to frustrate opponent attacks from unauthorized access. Digital images are exchanged over various types of networks related to a number of purposes. The data to be transmitted may be very confidential in nature. Many encryption methods are now available to encrypt and decrypt confidential data's[2].Here we uses a block cipher, a modified DES algorithm, which is enhanced by implementing pipelining concept and skew core key scheduling to encrypt images which provide faster encryption rates and high throughput. The hardware implementation of the design is also made and compared with various FPGA devices. Copyright © 2012 ACM.

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Publication Type: Journal Article

Year of Publication Title

2018

A. Ajith, Nambiar, N. Mohan, VP, A., Ajit, A., Remya Ajai A. S., and Ramachandran, R., “SAKSHA-Self Automated Kinematic Smart Haptic Arm”, Procedia Computer Science, vol. 133, pp. 711 - 717, 2018.[Abstract]


Robotics is the engineering branch which deals with robots and its technologies. Developing new technologies that exhibit unique, versatile, user friendly, redundant data, instrument and software is the prime motive behind robotics. Researchers who work in this area focus on automating a particular task by conferring information about the environment to the robotic arm through sensors, while others are concerned in implementing analytical concepts in robotics. Present day the industries are mainly working with the help of robotic machineries, which is used in all kind of manufacturing factories. This paper introduces a master slave robotic arm-‘SAKSHA’. SAKSHA is a controller for an industrial robotic arm which can be used in factories, medical field and manufacturing companies. The device can replace the present version of controllers which are used in industries, make them easy to use and precise. The design removes the complexity of programming a robotic arm in doing multiple tasks at a time. The main intention on developing this device is to reduce the gap between robots and humans.

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2015

A. Chandran and Remya Ajai A. S., “VLSI implementation of PASSERINE public key encryption algorithm”, International Journal of Applied Engineering Research, vol. 10, no. 55, pp. 128-131, 2015.[Abstract]


PASSERINE is a light weight encryption mechanism which can be implemented in resource constrained devices like RFID tags, sensor nodes etc. It is a hybrid form of Rabin public key encryption and Shamir’s randomized multiplication. Computationally demanding public modulus in Rabin encryption is replaced by randomized multiplication. There is only small integer arithmetic based on Chinese Reminder Theorem (CRT) in PASSERINE public key operation. Hence it has reduced latency and consumes very less hardware and software spaces when compared to RSA and Elliptical Curve Cryptography with same security level. This paper deals with FPGA implementation of PASSERINE public key operation. Implementation is done in Xilinx’s Virtex 5 FPGA. FPGA implementation has several advantages over existing microcontroller implementation. Private key operation has almost same complexity when compared to RSA algorithm.

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2012

Remya Ajai A. S. and Nagaraj, N., “A Novel Methodology for Memory Reduction in Distributed Arithmetic Based Discrete Wavelet Transform”, Procedia Engineering, vol. 30, pp. 226–233, 2012.[Abstract]


<p>Discrete Wavelet Transform (DWT) is widely used in image compression standards such as JPEG 2000. DWT can be implemented on FPGA using parallel Distributed Arithmetic (DA) architecture, which is suitable for low power implementation. However, the size of the memory in DA increases with the number of wavelet coefficients. In this paper, we propose a novel methodology to reduce the size of the Look-Up Tables (LUTs) used in DA for DWT. The table entries are sorted using Burrows-Wheeler Transform (BWT) and then compressed. The compressed table is stored in memory. During DWT/IDWT computation, without reconstructing the entire table we can recover only the required table entry. A comparative study of this methodology among different wavelets is performed. We demonstrate that the method is very effective for reducing the memory of DA architectures. A compression ratio of around 2.3:1 is achieved for the look-up table which stores the inner product of high-pass filter coefficients of Daubechies-4 (Db4) wavelet which is used in JPEG2000.</p>

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2012

P. Va Sruthi, Poornachandran, Pb, and Remya Ajai A. S., “Performance analysis and improvement using LFSR in the pipelined key scheduling section of DES”, Communications in Computer and Information Science, vol. 335 CCIS, pp. 215-224, 2012.[Abstract]


In this paper, DES algorithm is implemented by applying pipelining concept to the key scheduling part. Using this implementation, it is possible to have the key length equal to data length; which further improves the security of the system, at the same time decaying the performance. This scenario is similar to that of one time pad. i.e, here key storage and transmission is going to occupy more area and power, degrading the performance of the system. The security vs performance trade off is analyzed for the circuit. Another solution is also introduced in this paper, i.e, the Linear Feedback Shift Registers(LFSRs). Using LFSR, it is possible to have different keys generated every clock cycles, improving the security of the system, at the same time we need to store or transmit the single seed of LFSR only. The design is implemented in Virtex 5 FPGA device using Xilinx 12.1 platform. An encryption rate of 35.5 gbits/S is obtained, which is almost the fastest among all other current implementations. The performance of the system in terms of area, power and timing is analyzed using the Synopsys tool. © 2012 Springer-Verlag.

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2012

Remya Ajai A. S., Rajan, L., and Shiny, C., “VLSI implementation of Burrows wheeler transform for memory reduced distributed arithmetic architectures”, Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering, vol. 108 LNICST, pp. 242-245, 2012.[Abstract]


Multiply and accumulate function is the important part of digital signal processing algorithms. This can be implemented more effectively with distributed arithmetic (DA) architecture [1]. These architectures make extensive use of look-up tables, which make them ideal for implementing digital signal processing functions on Xilinx FPGAs. An emerging arithmetic-intensive digital signal processing algorithm is the discrete wavelet transform (DWT) which have proven to be extremely useful for image and video coding applications like MPEG-4 and JPEG 2000[2]. But the limitation of this architecture is that the size of look-up tables get increased exponentially as the constant coefficients of wavelet used for these applications increases. In this paper, we proposed a novel methodology to implement the Burrows wheeler transform (BWT) [3] block in FPGA for achieving memory reduced DA. © 2012 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering.

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2011

Remya Ajai A. S., Benny, A. S., A, J., and Shabana, K. M., “Microcontroller Based Sensor Network for Irrigation in Agriculture”, Global Journal of Engineering and Applied Sciences 2011, vol. 1, no. 3, pp. 53-56, 2011.