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Publication Type : Journal Article
Publisher : International Journal of Applied Engineering Research,
Source : International Journal of Applied Engineering Research, Volume 10, Issue 55, p.128-131 (2015)
Campus : Amritapuri
School : School of Engineering
Department : Electronics and Communication
Year : 2015
Abstract : PASSERINE is a light weight encryption mechanism which can be implemented in resource constrained devices like RFID tags, sensor nodes etc. It is a hybrid form of Rabin public key encryption and Shamir’s randomized multiplication. Computationally demanding public modulus in Rabin encryption is replaced by randomized multiplication. There is only small integer arithmetic based on Chinese Reminder Theorem (CRT) in PASSERINE public key operation. Hence it has reduced latency and consumes very less hardware and software spaces when compared to RSA and Elliptical Curve Cryptography with same security level. This paper deals with FPGA implementation of PASSERINE public key operation. Implementation is done in Xilinx’s Virtex 5 FPGA. FPGA implementation has several advantages over existing microcontroller implementation. Private key operation has almost same complexity when compared to RSA algorithm.
Cite this Research Publication : A. Chandran and Remya Ajai A. S., “VLSI implementation of PASSERINE public key encryption algorithm”, International Journal of Applied Engineering Research, vol. 10, no. 55, pp. 128-131, 2015.