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Effective implementation of des algorithm for voice scrambling

Publication Type : Conference Paper

Publisher : Springer

Source : Communications in Computer and Information Science, Volume 335 CCIS, Trivandrum, p.75-84 (2012)

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Keywords : Algorithms, Configurable Logic Blocks, Cryptography, Field programmable gate arrays (FPGA), Field-programming gate arrays, Hardware, High security environment, Network security, Pipe linings, Scheduling, Scrambling, Scrambling algorithm, Skew core, Speech signals

Campus : Amritapuri

School : School of Engineering

Center : Cyber Security

Department : Electronics and Communication

Year : 2012

Abstract : This paper presents a high performance reconfigurable hardware implementation of speech scrambling-descrambling system which can be used for military and high security environments. The scrambling algorithm is based on DES algorithm with a novel skew core key scheduling. The scrambled speech signal is not intelligible to the listener, but the recovered audio is very clear. This type of encryption can be used in applications where we need to discourage eavesdropping from co-channel users or RF scanners. The DES design is implemented on Virtex 5 XC5VLX110T Field Programming Gate Arrays (FPGA) technology. Final 16-stage pipelined design is achieved with encryption rate of 35.5 Gbit/s and 2140 number of Configurable logic blocks (CLBs). © 2012 Springer-Verlag.

Cite this Research Publication : J. Ea John, Ajai, A. SaRemya, and Poornachandran, Pb, “Effective implementation of des algorithm for voice scrambling”, Communications in Computer and Information Science, vol. 335 CCIS, pp. 75-84, 2012.

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