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Publication Type : Journal Article
Publisher : Procedia Engineering
Source : Procedia Engineering, Elsevier, Volume 30, p.226–233 (2012)
Campus : Amritapuri
School : School of Engineering
Department : Electronics and Communication
Year : 2012
Discrete Wavelet Transform (DWT) is widely used in image compression standards such as JPEG 2000. DWT can be implemented on FPGA using parallel Distributed Arithmetic (DA) architecture, which is suitable for low power implementation. However, the size of the memory in DA increases with the number of wavelet coefficients. In this paper, we propose a novel methodology to reduce the size of the Look-Up Tables (LUTs) used in DA for DWT. The table entries are sorted using Burrows-Wheeler Transform (BWT) and then compressed. The compressed table is stored in memory. During DWT/IDWT computation, without reconstructing the entire table we can recover only the required table entry. A comparative study of this methodology among different wavelets is performed. We demonstrate that the method is very effective for reducing the memory of DA architectures. A compression ratio of around 2.3:1 is achieved for the look-up table which stores the inner product of high-pass filter coefficients of Daubechies-4 (Db4) wavelet which is used in JPEG2000.
Cite this Research Publication : Remya Ajai A. S. and Nagaraj, N., “A Novel Methodology for Memory Reduction in Distributed Arithmetic Based Discrete Wavelet Transform”, Procedia Engineering, vol. 30, pp. 226–233, 2012.