Qualification: 
Ph.D
b_bala@cb.amrita.edu
Phone: 
+91 9943176560

Dr. B. Bala Tripura Sundari joined Amrita in 1998. She obtained her Ph. D. in the area of VLSI design from Amrita Vishwa Vidyapeetham in 2013, M. E. degree from PSG College of Technology, Bharathiar Coimbatore in 1998 and B. E. in Electronics and Communication, from A. C. C. Technology, Madurai Kamaraj University.

Her areas of interest include VLSI Design and VLSI signal processing for communication. She has guiding project for undergraduate students in the areas of VLSI design.

Dr. Bala is an IEEE member and holds membership in ISTE, IETE and Society for Failure Analysis (SFA). She is a reviewer of ITACT Journal of Microelectronics. She has contributed as Reviewer of ETRI Journal in 2013 and several international conferences in 2014. She Committee Member of Anna University.

Courses Handling

  • Digital Circuits and systems -B.Tech ECE and EIE

Research

Ongoing Guiding Ph. D.   

  • VLSI design for FIR filters area-VLSI signal processing
  • VLSI design for communication digital receiver
  • VLSI design for signal to noise improvement ,power improvement using modified adders and multipliers.

Publications

Publication Type: Conference Paper

Year of Publication Publication Type Title

2017

Conference Paper

S. Hariharan and Dr. Bala Tripura Sundari B., “Modeling 15nm graphene FET with contact resistance effects using channel segmentation technique”, in Proceedings of IEEE International Conference on Circuit, Power and Computing Technologies, ICCPCT 2017, 2017.[Abstract]


Graphene Field Effect Transistor (GFET) which is scaled down to 15nm is modeled by integrating the effects of contact resistance. The effect of contact resistance cannot be neglected as the device is scaled down. As the contact resistance is directly related to the device drain current, increase in contact resistance results in reduced current flow. In this paper contact resistance formula with respect to sheet resistance, resistivity of the graphene under source-drain contacts and channel length is derived. It is known that Gold (Au) offers lesser contact resistance due to its lower sheet resistivity. Hence the derived formula is validated by proving that the contact resistance of Gold(Au) is lesser than other metals. The derived formula provides easier contact resistance calculation by replacing the sheet resistivity of different materials. A comparative study is made by having different metals as contacts and the total contact resistance offered by each metal is estimated. The model that has been developed to incorporate the contact resistance is used to determine drain current, which is computed by analyzing the channel potential and electric field. A novel method is adopted to analyze the channel potential by segmenting the channel. This method is key feature in modeling a purely ballistic transport at 15nm channel length. The ballistic structure resulted in lower channel potential drop due to the reduced scattering of electrons. Mobility which is considered to be a key factor of Graphene is being analyzed with respect to carrier concentration, conductivity and temperature. The realized mobility is found to be higher of 2497 cm /Vs. Simulation of a digital application-GFET Inverter with lesser fall time is presented in this paper.

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2017

Conference Paper

Dr. Bala Tripura Sundari B. and Hariharan, S., “Modeling Graphene FET Frequency Doubler with Integrated Quantum Capacitance Effects using Guartic Equation Technique”, 2017.

2015

Conference Paper

Dr. Bala Tripura Sundari B. and R, S., “Compact model for switching characteristics of graphene”, in International Conference on Emerging Trends in Micro & Nanotechnology, 2015.

2015

Conference Paper

N. Srinivasan, Prakash, N. S., Shalakha, D., Sivaranjani, D., Dr. Bala Tripura Sundari B., and , “Power Reduction by Clock Gating Technique”, in International Conference on SMART GRID Technologies, Procedia Technology 21, 2015.[Abstract]


A continuous increase in the number of transistors mounted on a single chip brings about the need for power optimization. In this era, where technologies such as smart grid are developed, scope for power optimisation is increasing. Smart grid is an integration of essential building blocks such as sensor system, control units into existing power systems which could be implemented as a Silicon on Chip (SoC) in Very Large Scale Integration (VLSI) circuits. VLSI circuits can be both combinational and sequential. In sequential circuits clock is the major source of dynamic power consumption. The technique of clock gating is used to reduce the clock power consumption by cutting off the idle clock cycles. In this paper, we propose aVHDL-based technique, to insert clock gating circuit and also the dynamic power due to this is estimated. This model has been implemented onto ISCAS’89 sequential circuits that have been compiled using Modelsim Altera 13.1, and the Xilinx ISE tool is used to simulate and analyze power. The results show that the dynamic power is reduced for the sequential benchmark circuits considered.

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2011

Conference Paper

Dr. Bala Tripura Sundari B., “Dependence vectors and fast search of systolic mapping for computationally intensive image processing algorithms”, in IMECS 2011 - International MultiConference of Engineers and Computer Scientists 2011, Hong Kong, 2011, vol. 1, pp. 555-562.[Abstract]


2-D convolution in image processing and Full Search Block Motion (FSBM) estimation used in a H.264 video encoder, are highly data intensive and computationally intensive algorithms. Such algorithms require high memory access bandwidth due to repeated memory access. They are represented as nested do loop algorithms to enable systolic mapping. Mapping is used to facilitate the extraction of parallelism along with efficient data reuse. To enable the above, the dependence vector formulation and extraction of dependencies between iterations have been used. To implement the former the searching of scheduling vector t and Processor Matrix P is performed to form the mapping transformation matrix M. The focus of our work is the extraction of the dependence vectors from the application algorithm, followed by the search of the mapping matrix M, where a novel method of finding t vector has been used. This saves the search time as compared to the widely used exhaustive search methods. The resultant M matrix is used to arrive at the various design trade - offs. The method is applied to 2-D filtering algorithm and (FSBM) which act as good test cases for nested loop algorithms. The architecture is simulated and synthesized using Mentor Graphics tools and targeted to Virtex FPGA. More »»

Publication Type: Journal Article

Year of Publication Publication Type Title

2017

Journal Article

Dr. Bala Tripura Sundari B. and K Raj, A., “DC, Frequency Characterization of Dual Gated Graphene FET (GFET) Compact Model and its Circuit Application - Doubler Circuit”, IOP Conference Series: Materials Science and Engineering, vol. 225, p. 012016, 2017.[Abstract]


A Graphene FET(GFET) based on computational closed form expressions termed as compact model using quasi ballistic approach for circuit simulation is developed. The Verilog - A dual gated GFET model is developed for a channel length of 90 nm and a width of 1 μm and is found to have a better equivalent current and a higher Ion/Ioff ratio has been attained than the single gated model. It demonstrates the effect of body bias on the conductivity characteristics, as shown by the shift of the Dirac point. Also the frequency characterization of the model is obtained and verified by development of frequency multiplier circuits - doubler; the performance has been compared to have maintained in terms of spectral purity but having a better output amplitude validating the DC characteristics of the dual gated VS model used in the doubler circuit.

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2016

Journal Article

Dr. Bala Tripura Sundari B. and K., A. Raj, “Compact graphene field effect transistor modeling with quantum capacitance effects”, ARPN journal of engineering and applied sciences, vol. 11, no. 2, pp. 1347 – 1351, 2016.[Abstract]


A scaled down graphene field effect transistor (GFET) has been modeled by incorporating the quantum capacitance effects. The proposed GFET model scaled down to 90nm has been developed using compact model equations.Metal oxide gated compact GFET models have been modeled without considering variation of top gate capacitance with
quantum capacitance effects. But the effects of deviation of quantum capacitance become more with scaling down and cannot be neglected. In this paper the compact drain current equation has been derived by incorporating the dependence of quantum capacitance on the channel voltage and on intrinsic parameters of the device has been considered. The parameters of interest for circuit design have been determined from current characteristics, transfer characteristics, trans-conductance, and transit frequency. As the measure of performance of the model library in a circuit is often defined as unit gate delay, we propose to determine the rise time and fall time of a single GFET inverter and present the results.

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2016

Journal Article

Dr. Bala Tripura Sundari B. and K, R. Krishnanun, “High Level Synthesis for Design Space Exploration”, ARPN Journal of Engineering and Applied Sciences, vol. 11, pp. 1370-1375, 2016.

2016

Journal Article

S. Aravind, Shravan, S., Shrijan, S., R Sanjeev, V., and Dr. Bala Tripura Sundari B., “Simulation of Carbon Nanotube Field Effect Transistors using NEGF”, IOP Conference Series: Materials Science and Engineering, vol. 149, p. 012183, 2016.[Abstract]


A nearest neighbour tight binding approximation for analysing the I-V characteristics of ballistic CNTFETs is developed making use of the non-equilibrium green's function (NEGF) formalism. NEGF provides a matrix based computational since device description at the atomic level can be employed and multiple quantum phenomenon that are visible in real time can be effectively modelled. The proposed model involves zig-zag CNTs as the channel material with a 25nm channel length that uses a basis transformation to decouple the channel Hamiltonian. Temperature dependence on the output characteristics of CNTFETs with varying chirality is also studied. All simulations are carried out on MATLAB

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2015

Journal Article

Dr. Bala Tripura Sundari B. and Sreenath, R., “Modelling and Performance Comparison of Graphene and Carbon Nanotube Based FETs”, ARPN Journal of Engineering and Applied Sciences(Asian Research Publishing Network (ARPN)), vol. 10, pp. 4147-4154, 2015.[Abstract]


The era of nanoelectronics has emerged to overcome the effects of limits of physics due to technology scaling. Hence there is a need to explore the use of advanced nanomaterials namely, graphene and carbon nanotube that can overcome the limitations of short channel effects that arise in conventional silicon based field effect transistors (FET). The high carrier mobility of these materials on a substrate at room temperature and high electron velocity and thermal conductivity, are the motivation to explore the possibility to use FETs based on these materials. The focus in this work is the electronic characterization of such FET models. In this work, SPICE compactible models using closed form equations that are suitable for future circuit level simulations have been developed for single gate graphene FET (GFET), dual gate GFET (DG-GFET) and carbon nanotube field effect transistor (CNT-FET). This paper presents a modified single gate GFET model that is compatible with device length of 100nm and it is found to have better linear and saturation characteristics compared with the existing model. The modified GFET is found to have dirac point stability for lower values of drain to source voltage (Vds<0.4V) which is suitable for voltage scaling. A ballistic, non-linear piece-wise approximation approach in CNT-FET has been applied to achieve the saturation of drain current rather than using the computationally complex self-consistent field approach. This work also presents a detailed study of variation in transconductance and transit frequency for the modified GFET model and it is established to have a higher transit frequency at 100nm than the existing model. The simulation of models and comparison of various parameters are done using MATLAB.

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2015

Journal Article

Dr. Bala Tripura Sundari B. and Preethi, E. S., “Loop transformation for high level synthesis of iterative algorithms”, International Journal of Applied Engineering Research , pp. 31871-31882, 2015.[Abstract]


Digital signal processing applications (DSP) algorithms are iterative in nature and computationally intensive. Such computation-intensive procedures are represented by recursive equations and dependence graphs (DGs). Loops are the primary source of parallelism in iterative algorithm. For the purpose of throughput enhancement, loop transformation methods are commonly used in high-level synthesis. One of the most effective transformation techniques, named retiming, is a structural transformation that relocates the delays or registers in a circuit. This reduces the latency of the circuit without changing its functionality. Unfolding is another transformation technique used to improve the throughput of the system which when applied to DSP results in multiple iterations of the original program. Unfolding the program can also unearth buried concurrencies, leading to a drop in the iteration period and a proportionate increase in the throughput. The unfolding transformation is incorporated along with retimed DG to improve the parallel processing of the system. In this paper we have automated the modeling of DG and their transformation using high level language JAVA. The enhanced graphical user interface (GUI) and superior memory allocation system of JAVA make it ideal for such an application and for the realization of RTL generation of the unfolded and retimed DG of the benchmark circuits considered as the next phase of this work.

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2013

Journal Article

Dr. Bala Tripura Sundari B. and Padmanabhan, T. R., “A direct method for optimal VLSI realization of deeply nested n-D loop problems”, Microprocessors and Microsystems, vol. 37, pp. 610-628, 2013.[Abstract]


Many computationally intensive algorithms are often represented as n-dimensional (n-D) nested loop algorithms. Systolic-array-based projections and their modifications involving multidimensional vector space representations have been used to realise the optimal VLSI design of deeply nested loop problems. The approaches employed so far involve an extensive search of the feasible solution space through heuristic methods and yield near optimal solutions. This paper presents a method of identifying the optimal solution directly and through a logical procedure. The new allocation method is shown to evolve around the computational expression and the sub-space in which it lies. The array of processing elements termed as the PE array is allocated to the indentified computational sub-space which is strictly of lower dimension than the n-D problem space. The proposed new optimal allocation procedure is first explained using the 3-D matrix/matrix multiplication (MMM) problem. The effectiveness of the method for higher dimensional problem is demonstrated through the illustrative example flow of 6-D full search block motion (FSBM) algorithm. The various design possibilities of the above mapping procedure are explored analytically and the cost constraints termed the figure of merit (FoM) of the design are evolved for the various design trade-offs for MMM and 6-D FSBM problem. An experimental methodology is developed using a hyper-graph model to represent the PE allocation to a particular sub-space of the n-D problem space. The advantage of our mapping procedure is illustrated by considering two cases namely, first an allocation represented by a vertex cover that covers the nodes of the identified computational (n - x)-D sub-space, where x &lt; n, and in the second case as a random cover of group of nodes in the n-D problem space to model an allocation of PE array to a random sub-space. The design space exploration (DSE) results for the same are presented for the 6-D (FSBM) estimation algorithm using the high level synthesis tool 'GAUT' to compare the allocation of resources and utilisation in our method with the random PE array allocation and utilisation. It is found that our methodology leads to optimal number of resource allocation and their optimal utilisation for the various design possibilities using the timing constraint given as input to the HLS tool. Also the complexity of our approach is compared with that of existing methods which shows that the complexity of our approach does not grow with the n-D problem size. © 2013 Elsevier B.V. All rights reserved.

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2012

Journal Article

Dr. Bala Tripura Sundari B., “Design Space Exploration of Deeply Nested Loop 2D Filtering and 6 Level FSBM Algorithm Mapped Onto Systolic Array”, VLSI Design , vol. 2012, pp. 15:15–15:15, 2012.[Abstract]


The high integration density in today's VLSI chips offers enormous computing power to be utilized by the design of parallel computing hardware. The implementation of computationally intensive algorithms represented by n-dimensional (n-D) nested loop algorithms, onto parallel array architecture is termed as mapping. The methodologies adopted for mapping these algorithms onto parallel hardware often use heuristic search that requires a lot of computational effort to obtain near optimal solutions. We propose a new mapping procedure wherein a lower dimensional subspace (of the n-D problem space) of inner loop is identified, in which lies the computational expression that generates the output or outputs of the n-D problem. The processing elements (PE array) are assigned to the identified sub-space and the reuse of the PE array is through the assignment of the PE array to the successive sub-spaces in consecutive clock cycles/periods (CPs) to complete the computational tasks of the n-D problem. The above is used to develop our proposed modified heuristic search to arrive at optimal design and the complexity comparisons are given. The MATLAB results of the new search and the design space trade-off analysis using the high-level synthesis tool are presented for two typical computationally intensive nested loop algorithms--the 6D FSBM and the 4D edge detection alternatively known as the 2D filtering algorithm.

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2012

Journal Article

Dr. Bala Tripura Sundari B., “Design Space Exploration of Deeply Nested Loop 2-D Filtering and 6-level FSBM Algorithms Mapped onto Systolic Array”, The VLSI Design Journal, vol. 2012, 2012.

Publication Type: Conference Proceedings

Year of Publication Publication Type Title

2012

Conference Proceedings

Dr. Bala Tripura Sundari B. and Krishnan, V., “Comparison of configurations of data path architecture developed using template”, Advances in Intelligent Systems and Computing, vol. 174 AISC. Springer, Bangalore, Karnataka, India, pp. 539-548, 2012.[Abstract]


Data path circuits play a vital role in today's processors. Data path, which defines the structural model for interconnection of resources, needs to be flexible. It consists of a computing architecture modeled by a set of virtual templates. The focus of this work is to obtain the efficient configuration of the templates in order to map data intensive applications. The resource constrained scheduling process is employed to schedule the operations pertaining to different configurations. To achieve this scheduling, the data flow graph is modeled by grouping the resources for different configurations as a vertex cover model. Data intensive applications involve large amounts of data reuse and the number of registers and ports required is determined for each configuration. The number of registers, ports and latency are measures of efficiency of the configuration and using these measures the most efficient configuration of the templates to map an application is determined. © 2013 Springer. More »»

2011

Conference Proceedings

Ramesh S. R., Dr. Bala Tripura Sundari B., and .N, N., “Dataflow Transformation for Optimization of Digital/DSP Circuits”, Third National Conference on Recent Trends in Communication, Computation & Signal Processing organized by Department of ECE,Amrita School of Engineering, Ettimadai . 2011.

Publication Type: Book

Year of Publication Publication Type Title

2003

Book

T. R. Padmanabhan and Dr. Bala Tripura Sundari B., Design Through Verilog HDL. IEEE and John Wiley & Sons, 2003.

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