Publication

Abstract : As modern technology moves into dimensions of 14 nm and less, the size of transistors is decreasing and the number of transistors that are included in dense integrated circuits has generally doubled every two years throughout the history of computer technology. A dense design is more prone to faults. In that case, there is more chance of system behavior deviating from the expected. Thus, fault-tolerant systems play a crucial role in today's technology. A quad-model theory is adopted for fault-tolerant inverter creation, which replaces every transistor with four transistors. This technique addresses problems like stuck-at-1, stuck-at-0, and faults due to aging, radiation, and fabrication defects. Here the objective is to make the circuit continue its intended operation and obtain the desired output even if a part of the circuit fails. This theory ensures the continued operation at the cost of increased area. Here, the inverter is divided into two parts, namely the fault-tolerant inverter with isolation transistors and the second is the fault-tolerant inverter without isolation transistors. A fault-tolerant inverter with isolation transistors uses a basic quad-model theory with an isolation transistor placed between two neighbor transistors which share a source/drain in common. Also, we found the propagation delay of the inverters.