Course

1. RTL Modeling of Combinational Circuits using SystemVerilog
2. RTL Modeling of Sequential Circuits using SystemVerilog
3. Exploration of SystemVerilog Data Types and Constructs
4. Design and use of interface for Structured Connectivity
5. Introduction to Classes and Basic Object-Oriented Programming
6. Advanced OOP in SystemVerilog: Inheritance and Polymorphism
7. Concurrency and Inter-Process Communication: Mailboxes and Semaphores
8. Building a Layered Testbench for an Adder/Memory – Basic Driver and Stimulus
9. Layered Testbench with Monitors, Reference Models, and Scoreboards
10. Adding Assertions and Functional Coverage to SystemVerilog Testbench
11. Introduction to UVM: Testbench Architecture, Components, and Execution Flow
12. Hands-On UVM Lab: Building a Minimal UVM Testbench for a 4-bit Counter

NB: Scripting exercises with standard tools to be included wherever appropriate.

• To provide hands-on experience in functional verification of RTL designs using SystemVerilog.
• To develop skills in object-oriented programming and constrained random  verification
• To create scalable verification environments using SystemVerilog interfaces,

At the end of the course, the student should be able to

• CO1: Understand SystemVerilog RTL modeling and verification constructs
• CO2: Apply object-oriented programming to create reusable testbench components
• CO3: Analyze and verify DUT functionality using constrained random stimulus and interprocess communication techniques.
• CO4: Design and implement complete testbenches using interface-based and layered architecture

Skills Acquired:

• Design and verification of RTL modules in SystemVerilog
• Development of class-based testbenches using OOP
• Exposure to practical industry-standard verification flow

CO-PO Mapping:

1. Chris Spear and Greg Tumbush: SystemVerilog for Verification: A Guide to Learning the Testbench Language Features (4th Edition, 2020).
2. Ashok B. Mehta, Introduction to SystemVerilog: Simulation and Testbench Design (Springer, 2021).
3. Janick Bergeron, Writing Testbenches Using SystemVerilog (3rd Edition, Springer, 2016).
4. Ben Cohen, Srinivasan Venkataramanan, Ajeetha Kumari, Lisa Piper, SystemVerilog Assertions Handbook: For Design and Verification (4th Edition, 2019).