Course

Unit 1:

Introduction to STA – STA Concepts – Standard Cell Library – Pin Capacitance – Timing Modeling – Timing Models – Combinational and Sequential Cells – State Dependent Models – Advanced Timing Modeling – Power Dissipation Modeling – Other Attributes in Cell Library – Characterization and Operating Conditions – Interconnect Parasitics.

Unit 2:

Delay Calculation – Overview – Cell Delay using Effective Capacitance – Interconnect Delay – Slew Merging – Different Slew Thresholds – Different Voltage Domains – Path Delay and Slack Calculation – Crosstalk and Noise – Glitch Analysis – Delay Analysis – Computational Complexity – Noise Avoidance Techniques.

Unit 3 :

Configuring the STA Environment – Timing Verification – Setup and Hold Timing Check – Multicycle – False – Half Cycle Paths – Removal and Recovery Timing Checks – Timing Across Clock Domains – Multiple Clocks – Interface Analysis -On-Chip Variations- Time Borrowing- Back annotation-Sign-off Methodology- Statistical Static Timing Analysis.

Practical : EDA tools analysis – Setup and hold time violation and design remedies – Critical Path Analysis-Basic Clock Tree Synthesis flow- Determining Maximum frequency of operation

Course Objectives

• To introduce timing analysis and apply it to constrain a design.
• To impart knowledge on cell delay calculation and parasitic extraction.
• To provide a practical approach for configuring static timing environment.
• To analyze a timing report and check for timing violations.

Course Outcomes: At the end of the course, the student should be able to

• CO1: Understand the process of timing analysis in circuits and system design.
• CO2: Apply wire load models to compute the cell delay and slack.
• CO3: Analyze the circuit for design violations by configuring the timing environment.
• CO4: Evaluate the system and perform timing verification.

Skills Acquired: Practical knowledge on timing analysis of designs using standard tools like Synopsys Prime Time.

CO-PO Mapping:

1. J. Bhasker, R.Chadha, Static Timing Analysis for Nanometer Designs: A Practical
2. Approach, First edition, Springer, 2009.
3. Charles J. Alpert Dinesh P. Mehta Sachin S. Sapatnekar, Handbook of Algorithms for Physical Design Automation, First edition, CRC Press, 2008.
4. Himanshu Bhatnagar, Advanced ASIC Chip Synthesis Using Synopsys Design Compiler Physical Compiler and Prime Time, Second Edition, Springer, 2002.
5. Sridhar Gangadharan, Sanjay Churiwala, Constraining Designs for Synthesis and Timing Analysis: A practical Guide to Synopsys Design Constraints, Springer, 2015.
6. R.Jayagovwri, Pushpendra S Yadav, Static Timing Analysis for VLSI Circuits, Second Edition, Medtech, Scientific International Publisher,2024.