Year : 2025
Comparative Analysis of Modular Hybrid Adders in Radix-4 Booth Multiplier Architectures
Cite this Research Publication : Telluri Vani Sai Bhavani, Sonali Agrawal, C. Paramasivam, “Comparative Analysis of Modular Hybrid Adders in Radix-4 Booth Multiplier Architectures”, 9th International Conference on Electronics, Communication and Aerospace Technology [ICECA], 2025
Year : 2025
IDKLL-Based Logic Locking: Modified and Proposed Approaches Against SAT Attacks
Cite this Research Publication : Neha Bysani, Mohammed Aadil Siddiqui, Mallela Varshith, Sonali Agrawal, “IDKLL-Based Logic Locking: Modified and Proposed Approaches Against SAT Attacks”, 10th International Conference on Communication and Electronics Systems [ICCES], 2025.
Year : 2025
Performance Comparison of Advanced 32-bit ALU Architectures Using Optimized Adders
Cite this Research Publication : K. Sai Ganesh, Sonali Agrawal, Paramasivam C, “Performance Comparison of Advanced 32-bit ALU Architectures Using Optimized Adders”, 2nd International Conference on Information Technology, Electronics, and Intelligent Communication Systems, 2025.
Year : 2025
A Low-power, Area-efficient Leading Zero Counter
Cite this Research Publication : N. Hemanth, Sonali Agrawal, T.K. Ramesh, “A Low-power, Area-efficient Leading Zero Counter,” 6th International IEEE Conference on Computing, Communication and Networking Technologies (ICCCNT), 2025.
Year : 2025
A Resource-Efficient Hybrid Sorting Architecture Leveraging Even-Odd Merge Sorting Networks
Cite this Research Publication : Suhas J Reddy, Sonali Agrawal, T K Ramesh, “A Resource-Efficient Hybrid Sorting Architecture Leveraging Even-Odd Merge Sorting Networks,” 6th International IEEE Conference on Computing, Communication and Networking Technologies (ICCCNT), 2025.
Year : 2025
High-speed, Low-power, and Area-efficient CMOS Synchronous Up/Down Counter with Compact Toggle Flip-Flops
Cite this Research Publication : Krishna R Marar, L S Krishna Maanas, Sonali Agrawal, “High-speed, Low-power, and Area-efficient CMOS Synchronous Up/Down Counter with Compact Toggle Flip-Flops”, 6th International IEEE Conference on Computing, Communication and Networking Technologies (ICCCNT), 2025.
Year : 2025
Decoding Group Dynamics: A WhatsApp Chat Analysis Framework
Cite this Research Publication : Konapala Neehar Phani, Kalagara Sampah Raj, Marella V S S S Karthikeya, Vubbara Chaitri Reddy, Susmitha Vekkot, Sonali Agrawal, “Decoding Group Dynamics: A WhatsApp Chat Analysis Framework”, 6th International IEEE Conference on Computing, Communication and Networking Technologies (ICCCNT), 2025.
Year : 2025
Dynamic and Real-Time Network Packet Filtering Firewall System Using SystemVerilog: Design, Implementation, and Validation
Cite this Research Publication : Nimeshika T S R V S, Navyasree Katragadda, Abhinav Muraleedharan, P Hardik, Sonali Agrawal, “Dynamic and Real-Time Network Packet Filtering Firewall System Using SystemVerilog: Design, Implementation, and Validation”, 6th International IEEE Conference on Computing, Communication and Networking Technologies (ICCCNT), 2025.
Year : 2025
Comparative Analysis between Input Dependent Key Logic Locking (IDKLL) and SARLock for SAT Resistant Logic Locking
Cite this Research Publication : Neha Bysani, Varshith Mallela, Mohammed Aadil Siddiqui, Sonali Agrawal, Comparative Analysis between Input Dependent Key Logic Locking (IDKLL) and SARLock for SAT Resistant Logic Locking, 2025 3rd International Conference on Integrated Circuits and Communication Systems (ICICACS), IEEE, 2025, https://doi.org/10.1109/icicacs65178.2025.10967711
Publisher : IEEE
Year : 2025
Sign Language Recognition Using MobileNetV1: A Real Time Approach
Cite this Research Publication : Vempalli Hinduna Reddy, Nookala Sai Kovela, Neelima N, Sonali Agrawal, Sign Language Recognition Using MobileNetV1: A Real Time Approach, 2025 8th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), IEEE, 2025, https://doi.org/10.1109/iementech65115.2025.10959470
Publisher : IEEE
Year : 2025
Optimization of Insurance Claim Cost Prediction Through Health Data and Machine Learning
Cite this Research Publication : Shivram Mohan, Sanidhya Sharma, Sonali Agrawal, S Kamatchi, Optimization of Insurance Claim Cost Prediction Through Health Data and Machine Learning, 2025 Fifth International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT), IEEE, 2025, https://doi.org/10.1109/icaect63952.2025.10958928
Publisher : IEEE
Year : 2025
Algorithmic Approach to Controlled Deforestation: An Optimized Model for Ecological and Economic Outcomes
Cite this Research Publication : Bhavaraju Venkata Anagha, Krishna Tambatkar, Abhishek Ajay, Kamatchi S, Sonali Agrawal A, Algorithmic Approach to Controlled Deforestation: An Optimized Model for Ecological and Economic Outcomes, 2025 8th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), IEEE, 2025, https://doi.org/10.1109/iementech65115.2025.10959152
Publisher : IEEE
Year : 2024
TSPC STC-DET Flip-Flop With Autogated Clock Gating For Low-Power
Cite this Research Publication : Nazir Nadaf, Sonali Agrawal, TSPC STC-DET Flip-Flop With Autogated Clock Gating For Low-Power, 2024 8th International Conference on Electronics, Communication and Aerospace Technology (ICECA), IEEE, 2024, https://doi.org/10.1109/iceca63461.2024.10800954
Publisher : IEEE
Year : 2024
Comparative Analysis of High Stability Soft Error Aware 16T vs. 14T SRAM Cells
Cite this Research Publication : Krishna R Marar, L S Krishna Maanas, Sonali Agrawal, Comparative Analysis of High Stability Soft Error Aware 16T vs. 14T SRAM Cells, 2024 8th International Conference on Electronics, Communication and Aerospace Technology (ICECA), IEEE, 2024, https://doi.org/10.1109/iceca63461.2024.10800990
Publisher : IEEE
Year : 2024
Optimized Level Shifter with Logic Error Correction
Cite this Research Publication : Munnaluri Sai Ram, Vivek Marupudi, Sonali Agrawal, Optimized Level Shifter with Logic Error Correction, 2024 5th International Conference on Smart Electronics and Communication (ICOSEC), IEEE, 2024, https://doi.org/10.1109/icosec61587.2024.10722330
Publisher : IEEE
Year : 2024
K-degree Comparison-free Parallel Sorter with Duplicate Element Handler
Cite this Research Publication : Sahithi Gongada, Alluri Adharsh, Mannava Saket, Sonali Agrawal, K-degree Comparison-free Parallel Sorter with Duplicate Element Handler, 2024 5th International Conference on Smart Electronics and Communication (ICOSEC), IEEE, 2024, https://doi.org/10.1109/icosec61587.2024.10722670
Publisher : IEEE
Year : 2023
Design and Implementation of Low-Power and Area-Efficient Flip Flop with Redundant Pre-Charge Free Operation
Cite this Research Publication : R. Vishal, P. Sri Vidyanidhi, R. Deepak, Sonali Agrawal, Design and Implementation of Low-Power and Area-Efficient Flip Flop with Redundant Pre-Charge Free Operation, 2023 4th International Conference on Smart Electronics and Communication (ICOSEC), IEEE, 2023, https://doi.org/10.1109/icosec58147.2023.10276081
Publisher : IEEE
Year : 2023
Low-Power and Area-Efficient M-Term Binary Polynomial Multiplier for Finite Field
Cite this Research Publication : Sahishna Mulagaleti, Visakha Ravikumar, Sonali Agrawal, Low-Power and Area-Efficient M-Term Binary Polynomial Multiplier for Finite Field, 2023 4th IEEE Global Conference for Advancement in Technology (GCAT), IEEE, 2023, https://doi.org/10.1109/gcat59970.2023.10353369
Publisher : IEEE
Year : 2023
Integration of Open-Source Machine Learning Operations Tools into a Single Framework
Cite this Research Publication : T Vishwambari, Sonali Agrawal, Integration of Open-Source Machine Learning Operations Tools into a Single Framework, 2023 International Conference on Computing, Communication, and Intelligent Systems (ICCCIS), IEEE, 2023, https://doi.org/10.1109/icccis60361.2023.10425558
Publisher : IEEE
Year : 2023
Design and Implementation of Optimized Binary Counters and Compressors
Cite this Research Publication : Satya Sita Rama Sastry Iruvanti, Sonali Agrawal, Susmitha Vekkot, Design and Implementation of Optimized Binary Counters and Compressors, 2023 2nd International Conference on Futuristic Technologies (INCOFT), IEEE, 2023, https://doi.org/10.1109/incoft60753.2023.10425730
Publisher : IEEE
Year : 2022
A Novel Image Encryption using 3D Logistic Map and Improved Chirikov Map
Cite this Research Publication : Ch. Jnana Ramakrishna, D. Bharath Kalyan Reddy, B. Vishaal Bharadwaj, Sonali Agrawal, Ganapathi Hegde, A Novel Image Encryption using 3D Logistic Map and Improved Chirikov Map, 2022 International Conference on Advances in Computing, Communication and Materials (ICACCM), IEEE, 2022, https://doi.org/10.1109/icaccm56405.2022.10009076
Publisher : IEEE
Year : 2022
An Efficient Quasi Comparison-free Bidirectional Architecture for Sorting Algorithm
Cite this Research Publication : Gorrepati Chaithra Sri, S Arpitha Kopparthi Veera Hanuma, Nuthalapati Harshita, Sonali Agrawal, An Efficient Quasi Comparison-free Bidirectional Architecture for Sorting Algorithm, 2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT), IEEE, 2022, https://doi.org/10.1109/gcat55367.2022.9972111
Publisher : IEEE
Year : 2022
An Efficient Metal ECO Methodology for Addressing Timing Violations with 10X Turnaround Time
Cite this Research Publication : Sandeep Kumar Taumar, Sonali Agrawal, An Efficient Metal ECO Methodology for Addressing Timing Violations with 10X Turnaround Time, 2022 3rd International Conference on Smart Electronics and Communication (ICOSEC), IEEE, 2022, https://doi.org/10.1109/icosec54921.2022.9951989
Publisher : IEEE
Year : 2022
Low-power High-speed Folded MCML-based Frequency Divider for High-frequency Applications
Cite this Research Publication : Kurla Chandrika, Pooja R. B, Twihal P, Sonali Agrawal, Low-power High-speed Folded MCML-based Frequency Divider for High-frequency Applications, 2022 IEEE 2nd Mysore Sub Section International Conference (MysuruCon), IEEE, 2022, https://doi.org/10.1109/mysurucon55714.2022.9972577
Publisher : IEEE
Year : 2022
Power-Efficient Bulk-Driven MCML D-Latch for High-Frequency Applications
Cite this Research Publication : Manikantha Vallabhaneni, Sreenidhi Balki, P. S. V. N. K. Mani Gupta, Sonali Agrawal, Power-Efficient Bulk-Driven MCML D-Latch for High-Frequency Applications, Lecture Notes in Electrical Engineering, Springer Singapore, 2022, https://doi.org/10.1007/978-981-16-8862-1_49
Publisher : Springer Singapore
Year : 2021
Design, Implementation and Performance Comparison of D-Latch Using Different Topologies
Cite this Research Publication : P. S. V. N. K. Gupta, Balki, S., Vallabhaneni, M., and Agrawal, S., “Design, Implementation and Performance Comparison of D-Latch Using Different Topologies”, in 6th International Conference on Communication and Electronics Systems (ICCES) 2021, PPG Institute of Technology , Coimbatore , 2021.
Year : 2020
Multipumping-Enabled Multiported SRAM Based Efficient TCAM Design
Cite this Research Publication : A. Santhosh and S. Agrawal, “Multipumping-Enabled Multiported SRAM Based Efficient TCAM Design”, in 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), Kolkata, India, 2020.
Publisher : 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech)
Year : 2020
An Efficient Sorting Techniques for Priority Queues in High-Speed Networks
Cite this Research Publication : U. Meenakshi, Aishwarya, P. M., R. Keerthi, V., and S. Agrawal, “An Efficient Sorting Techniques for Priority Queues in High-Speed Networks”, in 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA), Coimbatore, India, 2019.
Publisher : 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA)
Year : 2020
Efficient Floating-Point HUB Adder For FPGA
Cite this Research Publication : M. Lahari and S. Agrawal, “Efficient Floating-Point HUB Adder For FPGA”, in 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), Kolkata, India, 2020.
Publisher : 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech)
Year : 2020
Analysis of High Speed Radix-4 Serial Multiplier
Cite this Research Publication : B. V. N. Tarun Kumar, Chitiprolu, A., G Reddy, H. Kumar, and S. Agrawal, “Analysis of High Speed Radix-4 Serial Multiplier”, in 2020 Third International Conference on Smart Systems and Inventive Technology (ICSSIT), Tirunelveli, India, 2020.
Publisher : 2020 Third International Conference on Smart Systems and Inventive Technology (ICSSIT)
Year : 2020
Design and Implementation of Power Efficient and fast Full Adders Using Hybrid Logics
Cite this Research Publication : S. Vamsi Ch, Kasyap, S. Aravind, S, S., and Agrawal, S., “Design and Implementation of Power Efficient and fast Full Adders Using Hybrid Logics”, in Sixth International Conference on Emerging Research in Computing, Information, Communication and Applications, ERCICA 2020, Nitte Meenakshi Institute of Technology, Bangalore, 2020.
Publisher : Nitte Meenakshi Institute of Technology, Bangalore
Year : 2019
Design of Power Efficient Fault Tolerant Registers using Modified Hybrid Protection Technique
Cite this Research Publication : M. M. Katti and S. Agrawal, “Design of Power Efficient Fault Tolerant Registers using Modified Hybrid Protection Technique”, in 2019 3rd International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), Kolkata, India, 2019.
Publisher : 2019 3rd International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech),
Year : 2019
Design of Efficient 2–4 Modified Mixed Logic Design Decoder
Cite this Research Publication : R. Kumar Arya and S. Agrawal, “Design of Efficient 2–4 Modified Mixed Logic Design Decoder”, in 2019 International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, 2019.
Publisher : 2019 International Conference on Communication and Electronics Systems (ICCES)
Year : 2019
A Robust Code for MBU Correction Till 5-Bit Error
Cite this Research Publication : S. K. Karan, Srikanth, N., and S. Agrawal, “A Robust Code for MBU Correction Till 5-Bit Error”, in 2019 International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, 2019.
Publisher : 2019 International Conference on Communication and Electronics Systems (ICCES)
Year : 2019
Zynq FPGA based system design for video surveillance with sobel edge detection
Cite this Research Publication : S. Eetha, S. Agrawal, and Neelam, S., “Zynq FPGA based system design for video surveillance with sobel edge detection”, in Proceedings - 2018 IEEE 4th International Symposium on Smart Electronic Systems, iSES 2018, 2019, pp. 76-79
Publisher : Proceedings - 2018 IEEE 4th International Symposium on Smart Electronic Systems, iSES 2018
Year : 2018
High speed, Low power Approximate Multipliers
Cite this Research Publication : K. R. Varma and S. Agrawal, “High speed, Low power Approximate Multipliers”, in 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI), Bangalore, India, 2018.
Publisher : 2018 International Conference on Advances in Computing, Communications and Informatics
Year : 2018
Efficient Dynamic Virtual Channel Architecture for NoC Systems
Cite this Research Publication : P. Avani and S. Agrawal, “Efficient Dynamic Virtual Channel Architecture for NoC Systems”, in 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI), Bangalore, India, 2018.
Publisher : 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI),
Year : 2018
High Speed Low Power Approximate Multiplier
Cite this Research Publication :
Publisher : Symposium on VLSI Design and Embedded Computing (VDEC’18), co-affiliated with Seventh International Conference on Advances in Computing, Communications and Informatics (ICACCI-2018)
Year : 2018
Efficient dynamic Virtual Channel architecture for NoC
Cite this Research Publication :
Publisher : Symposium on VLSI Design and Embedded Computing (VDEC’18), co-affiliated with Seventh International Conference on Advances in Computing, Communications and Informatics (ICACCI-2018)
Year : 2017
RSA Cryptosystem with Modified Montgomery Modular Multiplier
Cite this Research Publication : P. Priyadarsi Mahapatra and S. Agrawal, “RSA Cryptosystem with Modified Montgomery Modular Multiplier”, in 2017 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), Coimbatore, India, 2017.
Publisher : 2017 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)
Year : 2017
A Speed Efficient FIR Filter for Reconfigurable Applications
Cite this Research Publication : N. V. Menon and S. Agrawal, “A Speed Efficient FIR Filter for Reconfigurable Applications”, in 2017 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), Coimbatore, India, 2017.
Publisher : 2017 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)
Year : 2017
Low power VLSI architecture for combined FMO/Manchester encoder for reusability and FMO/Manchester codecs
Cite this Research Publication : N. Sowjith, K. Sandeep, S., Sumanth, M., and S. Agrawal, “Low power VLSI architecture for combined FMO/Manchester encoder for reusability and FMO/Manchester codecs”, in 2016 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2016, 2017.
Publisher : 2016 IEEE International Conference on Computational Intelligence and Computing Research,
Year : 2016
A fast architecture for maximum/minimum data finder with address from a set of data
Cite this Research Publication : S. V. Smrithi and S. Agrawal, “A fast architecture for maximum/minimum data finder with address from a set of data”, in 2016 International Conference on Computer Communication and Informatics, ICCCI 2016, 2016.
Publisher : International Conference on Computer Communication and Informatics, ICCCI 2016, Institute of Electrical and Electronics Engineers Inc
Year : 2016
An architecture for high speed Radix10 division
Cite this Research Publication : N. S., S. Agrawal, and Dr. N.S. Murty, “An architecture for high speed Radix10 division”, in 2016 International Conference on Computer Communication and Informatics (ICCCI), 2016.
Publisher : 2016 International Conference on Computer Communication and Informatics (ICCCI)