Sonali Agrawal currently serves as Assistant Professor(Sr. Gr.) at department of Electronics and Communication,Amrita School of Engineering, Banglore campus.


Publication Type: Conference Paper

Year of Publication Title


K. R. Verma and S. Agrawal, “High Speed Low Power Approximate Multiplier”, in Symposium on VLSI Design and Embedded Computing (VDEC’18), co-affiliated with Seventh International Conference on Advances in Computing, Communications and Informatics (ICACCI-2018), PES Institute of Technology, Bengaluru, South Campus, India, 2018.


Avani P. and S. Agrawal, “Efficient dynamic Virtual Channel architecture for NoC”, in Symposium on VLSI Design and Embedded Computing (VDEC’18), co-affiliated with Seventh International Conference on Advances in Computing, Communications and Informatics (ICACCI-2018), PES Institute of Technology, Bengaluru, South Campus, India, 2018.


N. Sowjith, K. Sandeep, S., Sumanth, M., and S. Agrawal, “Low power VLSI architecture for combined FMO/Manchester encoder for reusability and FMO/Manchester codecs”, in 2016 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2016, 2017.[Abstract]

The VLSI architecture for the low power combined FM0 and Manchester encoder (SOLS) circuit using modified GDI has been proposed in this paper. Comparisons are made with existing architecture using general CMOS Logic. The power consumption and delay in this circuit are reduced. The working conditions for existing circuit for FMO/Manchester encoder and decoder using HCPM technique have also been modified in this paper. The architecture has been realized in CMOS 90 nm technology. Cadence Virtuoso Analog design environment has been used for implementing and synthesizing the test circuits. © 2016 IEEE.

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N. S., S. Agrawal, and Dr. N.S. Murty, “An architecture for high speed Radix10 division”, in 2016 International Conference on Computer Communication and Informatics (ICCCI), 2016.[Abstract]

Decimal arithmetic is gaining more and more importance in business, commercial and financial applications due to error free and high speed computations. In this work, high speed radix10 divider architecture has been proposed to reduce the delay. This paper presents a modified architecture in which intermediate results are utilized to perform the high speed division. The modified architecture is simulated for different numbers of bits. Synthesis results show that the modified architecture implemented in 180nm technology has reduced delay when compared to digit recurrence with constant digit selection function architecture which is the fastest of existing architectures. More »»


S. V. Smrithi and S. Agrawal, “A fast architecture for maximum/minimum data finder with address from a set of data”, in 2016 International Conference on Computer Communication and Informatics, ICCCI 2016, 2016.[Abstract]

Real-time systems handle data in binary form and these systems should be catered with efficient circuits for fast data accessing and data processing. In this paper, a high speed architecture has been proposed to determine both the value and the address of the maximum/minimum element from an nelement set of k-bit size. The proposed solution performs the data finder and address finder operations in parallel resulting into a low latency and high throughput architecture. This architecture can also be used to determine the total number of occurrences of maximum/minimum with a priority scheme included for the position determination. Synthesis results obtained with 180-nm CMOS standard cell technology for different n and k, show an average of 70% improvement in speed for the proposed architecture when compared with related architectures. More »»

Publication Type: Journal Article

Year of Publication Title


N. Dohare and S. Agrawal, “APB based AHB interconnect testbench architecture using uvm_config_db”, International Journal of Control Theory and Applications, vol. 9, pp. 4377-4392, 2016.[Abstract]

This paper presents object-oriented testbench architecture for APB based AHB interconnect which is based on universal verification methodology (UVM) to build an efficient and structured verification environment. UVM-SV based AHB System that follows AHB Protocol, consists three AHB master, four AHB slave, an AHB interconnect (Design Under test) and one APB configure model which communicate with each other on the AHB bus and APB configure model decodes slave address range and generates signals for slave selection reduces interface complexity. System verilog interfaces in the testbench and DUT and virtual interfaces in the class based test environment cannot make use of type parameterize, results in very cumbersome code. To overcome this problem, this paper is using approach of pushing the virtual interface into the configuration database from top-level using uvm_config_db to reuse verification test environment and APB based AHB interconnect functional model is implemented which is configured as UVM component from testbech using uvm_config_db. A uvm_config_db method allows reuse of UVM components easily and configures uniformly. This paper is showing how APB based AHB Interconnect testbench is build using a uvm_config_db. The simulations are done using Mentor Graphics advanced Questasim 10.0b simulator with UVM base class library version 1.1d. © International Science Press. More »»