Publication Type : Conference Paper
Publisher : International Conference on Computer Communication and Informatics, ICCCI 2016, Institute of Electrical and Electronics Engineers Inc
Source : 2016 International Conference on Computer Communication and Informatics, ICCCI 2016, Institute of Electrical and Electronics Engineers Inc. (2016)
ISBN : 9781467366793
Keywords : CMOS standard cell technology, Computer hardware description languages, Data accessing, Data handling, Data processing, High throughput, High-speed architectures, High-speed arithmetic, Information science, Interactive computer systems, Position determination, Priority schemes, Proposed architectures, Real time systems, Reconfigurable hardware
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2016
Abstract : Real-time systems handle data in binary form and these systems should be catered with efficient circuits for fast data accessing and data processing. In this paper, a high speed architecture has been proposed to determine both the value and the address of the maximum/minimum element from an nelement set of k-bit size. The proposed solution performs the data finder and address finder operations in parallel resulting into a low latency and high throughput architecture. This architecture can also be used to determine the total number of occurrences of maximum/minimum with a priority scheme included for the position determination. Synthesis results obtained with 180-nm CMOS standard cell technology for different n and k, show an average of 70% improvement in speed for the proposed architecture when compared with related architectures.
Cite this Research Publication : S. V. Smrithi and S. Agrawal, “A fast architecture for maximum/minimum data finder with address from a set of data”, in 2016 International Conference on Computer Communication and Informatics, ICCCI 2016, 2016.