Publication

Abstract : Full adder is majorly used as a basic component in various arithmetic applications in the fields of VLSI and DSP. Any improvement in the performance of the adder cell will impact the overall performance of the designed circuit. Power consumption and speed are two vital parameters in evaluating the performance of a given circuit, but conflicting design aspects. Full adders can be implemented using various logic design techniques. In this paper, various hybrid full adders are proposed using the conventional design and an alternative logic structure approach. The performance of the full adder circuits is evaluated and compared with the existing implementation by performing extensive simulations using Cadence Virtuoso and LTspice EDA tools in 45 nm process technology. The performance analysis shows that the proposed hybrid full adder is more optimized in power consumption and delay compared to conventional CMOS and other hybrid implementations.