Publications

Abstract : Adders and multipliers form the significant components in all kind of digital applications and has always been a thought-provoking topic for the researchers. Multiplication process will initially find out the set of partial products and then groups the partial products according to their respective bit positions and takes the summation. Among the phases of multiplication, partial product reduction tree consumes the maximum power and area as it is done using several adders. In this paper, a High Speed, Low Power Approximate Multiplier is proposed in which a new 4-2 compressor is being projected and is made use while performing vector merge addition after transforming the partial product terms to lead varying probability terms. Simulation results shows that the proposed Approximate Multiplier achieved 3.19% less Area, 53.74% less Delay, 3.79% less Power compared to Approximate Multiplier [6] and 31% less Area, 81.35% less Delay and 59.83% less Power compared to that of an Exact Multiplier. When we make use of Approximate Multipliers, there are likelihoods of error occurring in some cases. Hence approximate multipliers are suggested only for Error Resilient applications. Video compression, Digital Image processing and Test Data compression can be categorized as such applications. The proposed approximate multiplier takes less Power, Area and Time and also can be paralleled to the existing approximate multiplier algorithms. Hence for Error resilient application, it is always sagacious to use less power consuming constituents since power is a crucial one to save in the current scenario.