Qualification: 
M.E
b_karthigha@cb.amrita.edu

Karthigha Balamurugan received the B. E. degree from Bharathiar University, in 1998 and M. E. degree from Government College of Technology, Coimbatore, in 2007.She joined as Assistant Professor in the Department of Electronics and Communication Engineering, School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore, in 2007. She is a member of IETE (Institution of Electronics and Telecommunication Engineers). She is currently pursuing her Ph. D., in the field of RF IC designs. Her research interests and works are in and around designing millimeter wave transceiver circuits, testability and reliability circuits such as electrostastic protection designs and digital electronics. She is an aspirant learner of mapping relativity theory on physiological effects.

Education

  • Pursuing: Ph. D. in RF VLSI Design
    Amrita VishwaVidyapeetham
  • 2007: M. E. in VLSI Design
    Anna University, Government College of Technology, Coimbatore
  • 1998: B. E. in Electronics and Instrumentation Engineering
    Bharathiar University/Tamilnadu College of Engineering

Professional Experience

Year Affiliation
2007 - Present Assistant Professor (Sr. Gr.), Amrita Vishwa Vidyapeetham
Domain : Teaching

Academic Responsibilities

Position Class / Batch
Class Adviser 2017 – 21, 2018 - 22

Undergraduate Courses Handled

  1. Analog IC design
  2. Digital IC design
  3. Electronics Circuits - 1
  4. Linear Integrated Circuits
  5. Fundamentals of Electrical Engineering
  6. Electric Circuits
  7. VLSI Design
  8. VLSI Technology
  9. Biomedical Instrumentation

Post-Graduate / PhD Courses Handled

  1. Analog VLSI Design (VLSI Design)
  2. CMOS RF IC Design (VLSI Design)
  3. Low Power VLSI
  4. Solid State Device Physics (VLSI Design)

Innovations in Teaching - Learning

Innovation Method Description with Tools used
Simulating the theoretical problem solved in class and comparing PSPICE, HSPICE, Cadence

Organizing Faculty Development / STTP / Workshops /Conferences

Title Organization Period Outcome
One day workshop on,“The Art of Technical Paper Writing and Professional Ethics” Amrita School of Engineering October 16, 2014 PG students of 40 strength got benefited

Academic Research – PG Projects

SNo Name of the Scholar Programme Specialization Duration Status
1. Anu Ravindran VLSI Design RF IC design 2014-15 Completed
2. Becky Mary Ninan VLSI Design RF IC design 2015-16 Completed
3. Sivakumar N. VLSI Design Microwave circuits 2015-16  
4. Krishnapriya S. Kartha VLSI Design Reliability of RF circuits 2016-17 Completed
5. Sarika M. R. VLSI Design Microwave components and analog circuit design 2016-17 Completed
6. GaliBhavaChaitanya VLSI Design   2017-18 Completed
7. Ajay Rajulapati VLSI Design Microwave components and circuits 2017-18 Completed
8. Pilli Sathavardhana Rao VLSI Design Microwave components and circuits 2018-19 Ongoing
9. JaideepVarrier VLSI Design Analog circutis 2018-19 Ongoing
10. Goriparthi Pradeep VLSI Design Digital IC design 2018-19 Ongoing

Publications

Publication Type: Journal Article

Year of Publication Title

2017

S. Ankathi, Vignan, S., Athukuri, S., Mohan, S., Karthigha Balamurugan, and M. Devi, N., “A 5–7 GHz Current Reuse and Gm-Boosted Common Gate Low Noise Amplifier with LC based ESD Protection in 32 nm CMOS”, Analog Integrated Circuits and Signal Processing, vol. 90, pp. 573–589, 2017.[Abstract]


Scaling of minimum length of the MOSFET has improved its performance but has reduced the breakdown voltage which makes it prone to Electrostatic Discharge (ESD) damage. This work presents a low-power gm-boosted common gate (CG) ultra wideband (UWB) low noise amplifier (LNA) architecture, operating in the 5–7 GHz range, employing current-reuse technique with LC based Electrostatic Discharge (ESD) protection. Common gate topology supports wide band input matching and noise figure independent of operating frequency. A PMOS common source topology is used as the gm-boosting stage in order to reduce the noise figure and to remove the dependency of noise figure from the bias point. The gm-boosting stage and the amplifier share common bias current to reduce the power consumption of the LNA. A shunt inductor, series capacitor and power clamp are used for protecting the circuit from ESD damage. The ESD circuit is co-designed with the input matching network in order to reduce the area of the layout. The proposed topology has shown significant improvement in gain and noise figure with ESD protection.

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2016

A. Ravindran, Karthigha Balamurugan, and Dr. Jayakumar M., “Design of Cascaded Common Source Low Noise Amplifier for S-Band using Transconductance Feedback”, Indian Journal of Science and Technology, vol. 9, 2016.[Abstract]


Background/Objectives: Now-a-days advancements in CMOS technology increase the demand on transceiver design in the aspect of gain, linearity, power, re-configurability and cost-effectiveness. The performance of RF frontend of transceiver system using MOS device are excellent and found to be the par of 3-5 semiconductor technology. Methods/Statistical Analysis: The first component present in transceiver design is Low Noise Amplifier (LNA) which requires high gain, low noise, better input-output matching, low power, good linearity and stability. Trade off between these performances is more complex when transistors operate at reduced supply voltage and reduced power consumption. So many researchers focus to modify the existing topology by adding active/passive feedback elements and/or using current re-use inductors 2,3. But the latter, suffer from large power consumption. Moreover LNA using cascode configuration offers good gain with low power but the circuit has the limitation of output voltage swing 4. So the proposed work focuses on the design of LNA using transconductance feedback in Common Source (CS) configuration circuits. Findings: At RF frequencies, distributed parasitic of the device dominates thus altering the input-output matching characteristics which degrades gain, noise figure and stability of Low Noise Amplifier. So design of multistage LNA with feedback techniques is necessary to increase the gain. The transconductance feedback used in the design of LNA suits well for increase of gain provided if it is properly designed to ensure stability. The proposed work involves the design of MOS based low noise amplifier using single stage and cascaded Common Source (CS) configuration in S-band. By using the transconductance feedback in CS amplifier, the voltage gain is boosted. Using the extracted small signal equivalents, single stage and cascaded CS amplifier with the transconductance feedback are designed and analyzed. Importance of device parasitic like gate to source capacitance, gate to drain capacitance and the output resistance influence the loop gain. This is brought in the design and emphasizes on the proper utilization of these parasitic in LNA design with transconductance feedback. Using a standard 90 nm CMOS process, LNAs have been demonstrated for 2-GHz frequency (S-band) applications. Operated at a supply voltage of 0.6 V, the gain and noise figure of single stage CS LNA with transconductance feedback are observed to be 17.9 dB and 2.1 dB respectively. It is noted that nearly 17% gain improvement has been achieved with excellent input reflection coefficient of -54.8 dB and low power consumption of 2.92 mW. Similarly, for a cascaded CS amplifier when operated at 0.6V, it is observed that the gain and noise figure are found to be 13.6 dB and 2.38 dB respectively. It is noted that nearly 6.25% increase in gain is achieved with appealing reverse gain of -52. 8 dB when compared to cascaded CS circuit without transconductance feedback. Higher reverse gain ensures the stability of the designed amplifier. Applications: The proposed work is needed in the design of transceivers working at S-band (2 GHz - 8 GHz). Few noticeable applications are: Communication satellites (NASA), weather radar systems, microwave ovens and optical communication which require low power modules. Improvements: This work can be further extended to reconfigure the input matching network so that UWB bandwidth is covered.

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2015

Karthigha Balamurugan, M. Nirmala Devi, and Dr. Jayakumar M., “Performance analysis of 60 GHZ low noise amplifiers using multi-gate mosfets”, Journal of Theoretical and Applied Information Technology, vol. 77, pp. 373-381, 2015.[Abstract]


Short-channel devices are preferred for realizing millimetre circuits, but these are affected by the short- channel effects (SCE). Multi-Gate (MG) MOSFET is found to be an alternative to overcome this drawback. In this paper, study and analysis of DC and AC parameters of MG MOSFETs have been attempted and small signal gain (y21) of multi-gate structure is analytically derived. Design of low noise amplifier (LNA) at 60 GHz using the channel charging resistance model has been done.Small signal gain and noise figure using the channel charging resistance model has been derived and analysed. The proposed LNA circuit uses various multi-gate MOSFET structures and the results are compared with conventional MOSFET based design. The designed LNA using a Quadruple Gate structure exhibited the noise figure improvement of 24.4% and 42.79% when operated at 1 V and 1.5 V respectively. Also the corresponding gain increases by 2.38 times and 4.9 times compared with conventional single gate MOSFET design. © 2005 - 2015 JATIT & LLS. All rights reserved.

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2014

Karthigha Balamurugan, Dr. Nirmala Devi M., and Jayakumar, M., “Design of V-band low noise amplifier using current reuse topologies”, International Journal of Applied Engineering Research, vol. 9, pp. 27319-27330, 2014.[Abstract]


This paper presents the design of single stage, cascode Low Noise Amplifier (LNA) at V-band using current reuse topologies. First, the design of source inductor and gate inductor of cascode transistor are done by considering its small signal equivalents. For this, the output resistance, the internode resistance, the terminal and the gate-source capacitances of cascode amplifier are considered and exploited to determine the value of source and gate inductance. This results in compact and efficient LNA design. Compared to the conventional cascode design, the forward gains at 60 GHz using current reuse source inductor, gate inductor and its combination increases by 8.71%, 52.7% and 64.6% respectively. In second part, the proposed work describes the LNA circuit that uses the design of inductive load thereby achieving reduced VDD supply at common gate transistor. The forward gain and noise figure obtained from this method are 5.8 dB and 2.3 dB respectively. Power consumption of LNA design having inductive load is 7.43 mW that is comparatively lower than the conventional cascode design, which consumes 8.11 mW. For the two designs, IIP3 obtained are -3 dBm and -1 dBm respectively and found to be in good agreement with the expected response. © Research India Publications.

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Publication Type: Conference Paper

Year of Publication Title

2017

B. M. Ninan and Karthigha Balamurugan, “Design of CMOS Based Low Noise Amplifier at 60 GHz and it's Gain Variability Through Body Biasing”, in 2017 International Conference on Computer Communication and Informatics, ICCCI 2017, 2017.[Abstract]


This paper presents a low power, high gain low noise amplifier (LNA) design using current re-use inductors and complementary MOS structure. Gain variability has been achieved using forward body bias technique applied in the amplifying transistor. Using current re-use inductors at the drain of the complementary MOS structure, drain current is shared between PMOS and NMOS. The width of amplifying transistor is chosen to give minimum noise figure and good input matching. The observations show that the gain obtained by the proposed structure is 8.05dB with low noise figure of 2.14dB. The supply voltage used in the LNA design is 1.1V resulting in a power consumption of 2.607mW.

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2014

M. Archanaa and Karthigha Balamurugan, “Analysis of thermal noise and noise reduction in CMOS device”, in International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 , 2014.[Abstract]


Advanced CMOS technology assures CMOS device as a good choice for physical realization of RF applications. But as scaling progresses, noise and short channel effect start to deteriorate the device performance, thus increasing the power dissipation. This work focuses on the analysis of thermal noise by varying the gate resistance and frequency. Equivalent noise voltage is calculated for various extracted gate resistance and the effect of distributed gate resistance due to wider channel MOS is analyzed. Thermal noise is reduced using multifinger gate structure when compared to conventional nMOS. A complete small signal equivalent of nMOS along with augmented equivalent noise models is discussed. More »»

2014

S. Sarathkrishna, Karthigha Balamurugan, Dr. Nirmala Devi M., and Dr. Jayakumar M., “Design and Analysis of GaN HEMT based LNA with CPW matching”, in 2014 Eleventh International Conference on Wireless and Optical Communications Networks (WOCN), , 2014.[Abstract]


GaN based devices are in great demand due to its rugged characteristics at extreme conditions. In this paper, design of GaN monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA) with coplanar waveguide matching is presented to understand the key aspects of high gain, low noise figure and high linearity. The LNA can be used in base station technologies as frequency of interest is from 0.6-3 GHz. It delivers gain of 23 dB and noise figure 0.3 dB and OIP3 upto 51 dBm. The linear performance presented here enables reconfigurable designs of LNA over multiple octaves of bandwidth.

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2014

B. Vinod, Karthigha Balamurugan, and Dr. Jayakumar M., “Design of CMOS based reconfigurable LNA at millimeter wave frequency using active load”, in 2014 IEEE International Conference on Advanced Communication, Control and Computing Technologies, ICACCCT 2014, 2014, pp. 713-718.[Abstract]


Due to increased commercial and scientific applications in millimeter wave (mm wave) band, the development of mm wave transceivers is considered as prominent phase in RFIC design cycle. This paper proposes the design of reconfigurable low noise amplifier (LNA) working at 60 GHz using active load transistor. A single stage source degenerated LNA has been designed to achieve a gain of 8.38 dB and noise figure (NF) of 2.92 dB. The frequency of operation is tuned from 57 to 64 GHz i.e. at millimeter wave. Variation in gain and noise figure are achieved through the design of active load using NMOS transistor. This active load works as reconfiguration network which is subjected to proper bias voltage that yields the highest gain of 8.41 dB and the lower possible gain of 6.9 dB. Similarly the results of NF reaching 2.92 dB as minimum value and on the other end reaching 3.3 dB are observed and presented. That is, reconfigurable performance parameters are gain and NF whose variability is observed to be 17.66 % and 13% respectively. Proper bias voltage is extracted using DC characteristics of load transistor and their results are presented. Design parameter of LNA at millimeter wave frequencies, consideration of noise sources and its equivalent noise voltages, device modeling considering the parasitic effect and choice of LNA configuration have also been discussed. © 2014 IEEE.

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Publication Type: Conference Proceedings

Year of Publication Title

2016

B. M. Ninan, Karthigha Balamurugan, and Devi, M. N., “Design and Analysis of Low Noise Amplifier at 60 GHz using Active Feedback and Current Re-Use Topologies”, Proceedings of the 3rd International Conference on Devices, Circuits and Systems, ICDCS 2016. pp. 161-166, 2016.[Abstract]


The design and analysis of low power, low noise amplifier (LNA) using active feedback and current re-use topologies at 60 GHz have been attempted in this paper. A single stage, basic cascode LNA is designed and its small signal gain is analyzed. To improve small signal gain, simple active transistor feedback and cascode feedback structures are designed and added to the basic LNA. In addition to this, current re-use inductor is designed and added to the cascode amplifier which is intended to give low power and low noise figure. Small signal analysis of simple active transistor feedback and current re-use inductor has been presented. The results of three LNAs included with simple active transistor feedback, cascode feedback and current re-use inductor are analyzed. It is observed that the gain increases approximately by 21.4 %, 35.76 % and 50.1 % for LNA circuits with active transistor feedback, cascode feedback and current re-use topologies respectively when compared to basic cascode LNA. Noise figures of the above mentioned topologies are observed to be 1.1 dB, 1.15 dB and 46.1e-03 dB respectively and found to be promising when compared to basic structure which gives 1.87 dB. Power consumption of the above mentioned circuits are nearly equal to 7.14 mW.

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2014

J. Sirisha, C., N. Vaishnavi, P., N. K., S., S. Vidhya, G., Y., Karthigha Balamurugan, Dr. Nirmala Devi M., and M., J., “Study and Design of CMOS Based Millimeter Wave LNA Including Noise Models”, International Conference on Communication and Computing, ICC 2014. Elsevier, Bangalore, India, pp. 1-8, 2014.[Abstract]


A new flexible logic Built in Self-Test (BIST) scheme that has complete reconfigurability is presented. This technique uses a Linear Feedback Shift Register (LFSR), Multiple Input Signature Register (MISR) and a Bist controller; all of them programmable to work with any scan based design and targeted to detect all possible single stuck at faults. The seed activated LFSR generates exhaustive test patterns which are applied on any Design Under Test (DUT) and responses are received at the output of the scan chains in the DUT and the responses are compressed to produce a signature. It is shown that this scheme works with multiple designs without any structural modification in the BIST blocks. This technique is well suited to work with any scan based sequential design. A maximum number of 100 scan chains supported which can be increased. It eliminates the drawback of creating new bist logic for different blocks of a single System on Chip (SoC). Parallel testing of different blocks within a SoC is also possible within the power limits. The Reconfigurable Logic BIST (RLBIST) is checked in six designs and techniques are adopted to optimize the testpatterns with the help of cadence Encounter true time 13.1 ATPG. It is shown that the speed, power and area of the DUT are not affected by the reconfigurable BIST structures.

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2014

M. Archanaa, Karthigha Balamurugan, and Dr. Jayakumar M., “Design of MOS-based all-pass filter using thermal noise models”, 2014 International Conference on Embedded Systems (ICES), . IEEE-Explore, pp. 39-43, 2014.[Abstract]


Scaling of MOSFET increases the device performance in terms of speed, current drive, operating frequency and many other parameters; but on the other end, noise aggravates due to shrinking of device dimensions. Although several noise sources are present in recent submicron device, the equivalent thermal noise is considered as a prominent one. This paper deals with analysis and computation of various available thermal noise models and also focuses on the design and implementation of MOS-based all-pass filter using the appropriate thermal noise model. Thus the drawbacks of the currently available MOSFET models which do not include the equivalent noise model, have been considerably overcome. Simulation results of MOS based all pass filter with and without the inclusion of equivalent thermal noise model have been discussed and hence the accuracy of the design is improved.

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