Publication

Abstract : This paper presents the power efficient and high speed novel flash analog to digital converter. The present research uses a dynamic double tail comparator and efficient low power encoding scheme intended of ultra high frequency range (GHz) for 5-bit flash analog to digital converter. The adapted comparator is having facilities of low voltages and high sampling rate frequencies. Output of comparator block i.e. thermometer code to binary conversion block is more important because it consumes more power and speed of the circuit rebates. An encoder block in this paper is converting the thermometer code into the intermediate gray code using the merged DCVSL technique and gray code to binary code using Ex-OR logic block. The conversion of thermometer code to gray code used to rebate the bubble errors in the flash ADC. To maintain the low power dissipation with high speed, the implementation of the encoder is Merged DCVSLPG logic is presented in this paper. The used comparator and encoder implemented on CADENCE tool in 65nm technology with 0.8 V power supply. The simulation results of flash analog to digital converter average power consumption and delay is 16.33 mw and 1.542 ps. The power delay product (PDP) or Figure of merit (FOM) of the flash ADC is 25.18 fJ.