Course

Unit 1:

Introduction to VLSI Design Flow and HDLs –Verilog modeling styles – Gate Level – Structural – Dataflow –RTL Abstraction –RTL Design – Design and Synthesis of Logic Circuits with Verilog HDL.

Unit 2:

Sequential Building Blocks – Latch, Flip-flops – Registers – Shift Registers and Digital Counters – Sequential multiplier – Finite State Machines (FSM)– Types of FSM – Design and Implementation – Capabilities and limitations of FSM –Digital Subsystem Design – FIFOs – Memories –Buffers
Fundamental mode model – Flow table – State reduction Races, Cycles and Hazards.

Unit 3:

Case Study of Design and Modeling of a Simple Digital System – Datapath and Controller Design – Programmable Logic Devices – CPLD – FPGA – Verilog Design for FPGA Synthesis – Introduction to High Level Synthesis.

• To understand the flow of digital design at the RTL abstraction level with HDL.
• To explore HDL approaches for modeling combinational and sequential circuits
• To introduce design of different subsystems using HDL design flow.

At the end of the course, the student should be able to

• CO1: Ability to understand the HDL design flow and different modeling styles on hardware synthesis
• CO2: Ability to develop systems at the RTL abstraction layer.
• CO3: Ability to develop models for combinational and sequential blocks.
• CO4: Ability to model and evaluate architectures for digital systems.

Skills Acquired: Design and modeling system-level architectures at the RTL abstraction level, and implementing the design with FPGA resources.

CO-PO Mapping:

1. Michael D. Ciletti, Advanced Digital Design with Verilog HDL, Second Edition, Pearson Higher Education, 2011.
2. Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design, Third Edition, McGraw Hill, 2014.
3. Morris Mano and Michael D. Ciletti, Digital Design: With an Introduction to the Verilog HDL, Fifth Edition, Pearson Higher Education, 2013.
4. Peter Minns and Lan Elliott, FSMBased Digital Design Using Verilog HDL, Fifth Edition, John Wiley and Sons Ltd, 2008.
5. Scott Hauck and Andre` DeHon, “Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation”, Morgan Kaufmann, July 2010.
6. Stephen M. Trimberger, “Field – programmable Gate Array Technology”, Springer, 2007.