Course

Unit 1:

Programmable Logic Devices – PROM – PAL – PLA – CPLD – Gate Arrays – MPGA – PGA – Programming Technologies – EPROM – EEPROM – FLASH – SRAM – FPGA Fabric – Configurable Logic Block – LUT – Slice – Slicem – Programmable Interconnects – Input Output Blocks – Keeper Circuit – Xilinx 7 Series Architecture.

Unit 2:

FPGA Design Flow and Abstraction Levels – Verilog Design for Synthesis – One Hot Encoding – Memory Blocks – Block Memory Generator (BRAM/BROM) – Single Port Memory – Dual Port Memory – FIFO – Distributed RAM – Synthesis Pitfalls – Latch Inference – Static Timing Analysis – Speed Performance – Timing Constraints – Clock Management – Clock Buffers – Clock Tree Routing.

Unit 3:

Introduction to SoC Design – Hard Macros – Multipliers – DSP Block – Hard Core Processors – Interface Circuits – Configuration Chain – JTAG Interface – Zynq7000 Architecture.

Course Objectives

• To introduce the internal architecture of programmable logic with focus on FPGA.
• To provide knowledge in FPGA design flow at the architectural and system design.
• To impart a good background in block-based design using standard system level tools.

Course Outcomes: At the end of the course, the student should be able to

• CO1: Understand the structure of the fabric of programmable logic.
• CO2: Apply techniques for logic designing using field programmable devices.
• CO3: Analyze and comprehend FPGA design flow and related design, synthesis, and timing issues.
• CO4: Evaluate system level architectures by integrating IP cores, including softcore and hardcore processors.

Skills Acquired: Provide a practical approach for design of embedded systems using FPGAs.

CO-PO Mapping:

1. Amano, Hideharu, Principles and Structures of FPGAs, First Edition, Springer, 2018.
2. Readler, Blaine C., Verilog by example: a concise introduction for FPGA design, Full Arc Press, 2011.  
3. ZainalabedinNavabi, Embedded Core Design with FPGAs, First Edition, McGraw Hill, 2008.
4. Xilinx Inc, Vivado Design Suite User Guide, 2021.