Publication

Abstract : Different models of multiplier that offer the least power consumption are designed as technology node changes. The motive of the designers is to work on the minimization of power with less penalty in speed and area. The main focus of the present development is on the low power multiplier design for the different applications. This paper proposes a method of an efficient Wallace Tree Multiplier which is power efficient and uses a 7:3 counter consisting of full adders implemented using the NAND Logic cells. This proposed design is synthesized in the Cadence Genus tool which uses a 45 nm technology library cell in CMOS. The detailed comparison is performed between two multipliers in which one is designed using 2: 1 multiplexers and Exor gates that already exist and the other using NAND Logic cells which is proposed for 4-bit operands. The proposed design of the multiplier which uses NAND logic cells shows that it takes less power and has less delay when it is compared to the multiplier which uses 2: 1 Multiplexers and Exor gates. This design gives a good performance for both FPGA and ASIC platforms.