Publication

Abstract : In VLSI design, a synchronous binary counter is a fundamental part that is frequently utilized. A synchronous binary counter needs to be quick and able to accommodate a large bit width to be functional in a range of applications. However, extensive carry chains and large fan-outs were the main causes of low counting rates on most older counters, especially when the counter size was not modest. This study proposes a fast n-fold frequency divider that can be programmed. With sensible counter sizes, a newly adjusted counter is employed. To mitigate the fan-out problem in the modified counter, the 1-bit Johnson counter and pre-scalar counter are replicated. This helps to minimize the delay resulting from the increment, and the backward carry propagation technique (BCP) is utilized to eliminate the latency of ripple carry propagation. Regardless of counter size, custom counters obtain the highest rate of counting. An innovative and quick framework for synchronous binary counting is proposed in this executive summary.