Publication

Abstract : The core uses the RISC-V RV32I base integer instruction set architecture. RISC-V is an open standard ISA that is freely available for modification. To implement our processor core, we followed the FPGA design methodology. The RISC-V RV32I uses 32 instructions where each executes in 4 clock cycles. In this paper, we have used RV32I as reference and implemented 8-bit RISC-V processor for ALU operation. The 8-bit RISC-V ALU was implemented with the design being managed using the Verilog HDL while making use of 8-bit operands and a 4-bit control signal in carrying out multiple arithmetic and logical operations. The ALU is used for RISC-V implementation to run the instructions, such as adding/subtracting registers, and changing branches. A number of key performance optimizing techniques reduce latency, boost through, and handle division by zero. We have implemented the analysis in Vivado tool for the following reports-efficient power, thermal, and signal integrity, therefore making it ideal for applications in embedded systems. In the case of ALU, it consumes 6.917 W of on chip power and resource utilization is minimal thus making it more viable in IoT and automotive applications.