Course

A suitable low complex CUT can be considered for the entire flow. ASIC Frontend Flow Lab Experiments

1. Design of Digital Architecture for given specification ( Verilog/System Verilog based RTL coding and simulation of combinational and finite state machine based design) 
2. Logical Synthesis of Digital Architecture ( RTL to Gate level Netlist)
3. Functional Verification ( System Verilog based TB development)
4. Static timing Analysis (STA) ( set up/hold violation. Critical path analysis, Clock skew and uncertainty) ASIC Backend Flow Lab  Experiments
5. Floor planning (Floor plan layout files, Placement of macros, Pin Assignment. Power ring creation)
6. Placement and Clock Tree Synthesis (Placement optimization, Clock tree design, skew and latency reduction)
7. Routing (Routing congestion, and optimization, Later assignments and via usage, Routing DRC)
8. Post layout Verification (DRC and LVS Check).
9. Power planning and IR Drop (Power mess creation, IR drop distribution)
10. Parasitic Extraction and Post Layout STA (parasitic modelling, crosstalk and signal integrity, reverification after layout).

At the end of the course, the student should be able to

• CO1: To gain understanding of the detailed steps involved in FE and BE.
• CO2: Design ASIC based digital systems using industry standard EDA tools
• CO3: Design, simulate and synthesize complex digital system

Skills Acquired:

• ASIC based system designs using EDA tools
• Design and synthesis of complex digital systems

CO-PO Mapping:

1. Farzad Nekoogar, Faranak Nekoogar, “From ASICs to SOCs: A Practical Approach”, Pearson, 2003.
2. Luciano Lavagno, Louis Scheffer, and Grant Martin. EDA for IC Implementation, Circuit Design, and ProcessTechnology (Electronic Design Automation for Integrated Circuits Handbook). CRC Press, Inc., USA, 2006.
3. EDA manuals from Synopsys and Cadence
4. Stuart Sutherland, “RTL Modeling With System Verilog for Simulation and Synthesis: Using System Verilog for ASIC and FPGA Design”, Sutherland HDL Inc., 2017
5. Naveed Sherwani, “Algorithms for VLSI Physical Design Automation“, Kluwer Academic Publishers in 1993.