Syllabus
                                                
                             Unit I  
                            Introduction to logic circuits – Variables and functions, inversion – Truth tables – Logic gates and Networks – Boolean algebra – Synthesis using gates – Design examples – Optimized implementation of logic functions – Karnaugh map – Strategy for minimization – Minimization of product of sums forms – Incompletely specified functions – Multiple output circuits – Tabular method for minimization.
                         
                                                
                             Unit II   
                            Combinational circuit building blocks – Number representation and arithmetic circuits: Addition of unsigned numbers – Signed numbers – Fast adders – Multiplexers – Decoders – Encoders – Code converters – Arithmetic comparison circuits.
                         
                                                
                             Unit III   
                            Sequential circuit building blocks – Basic latch – Gated SR latch – Gated D latch – Master slave and edge triggered – D flip-flops – T flip-flop – JK flip-flop, Registers, Asynchronous Counters, Synchronous Counters, Ring Counter and Johnson Counter, Synchronous sequential circuits – Basic design steps – State assignment problem – Design of Mealy and Moore state models.
                         
                                                                     
                                                            
                                                    
                            Objectives and Outcomes
                            
                                Course Objectives
- To provide an understanding of basic building blocks of digital circuits
 
- To enable the understanding of Boolean algebra and logic function optimization
 
- To enable design of combinational and sequential circuits
 
Course Outcomes 
CO1: Realize a given expression in terms of basic building blocks.
CO2: Minimize a given logic expression.
CO3: Design combinational circuits
CO4: Design Sequential circuits.
 CO-PO Mapping 
| PO/PSO | 
PO1 | 
PO2 | 
PO3 | 
PO4 | 
PO5 | 
PO6 | 
PO7 | 
PO8 | 
PO9 | 
PO10 | 
PO11 | 
PO12 | 
PSO1 | 
PSO2 | 
| CO | 
| CO1 | 
3 | 
2 | 
 | 
 | 
 | 
 | 
 | 
 | 
 | 
 | 
 | 
 | 
 | 
2 | 
| CO2 | 
3 | 
2 | 
 | 
 | 
 | 
 | 
 | 
 | 
 | 
 | 
 | 
 | 
 | 
2 | 
| CO3 | 
3 | 
3 | 
2 | 
 | 
 | 
 | 
 | 
 | 
 | 
 | 
 | 
2 | 
 | 
2 | 
| CO4 | 
3 | 
3 | 
2 | 
 | 
 | 
 | 
 | 
 | 
 | 
 | 
 | 
2 | 
 | 
2 | 
 
                             
                             
                                                    
                            Evaluation Pattern
                            
                                Evaluation Pattern: 60:40
| Assessment | 
Internal | 
External | 
| Mid Sem Examination | 
30 | 
 | 
| *Continuous Assessment (CAT) | 
30 | 
 | 
| End Semester | 
 | 
40 | 
 
*CAT includes Quizzes, Assignments and Tutorials
                             
                             
                                                    
                            Text Books / References
                            
                                Textbook(s)
Stephen Brown, Zvonko Vranesic, “Fundamentals of Digital logic with Verilog Design”, Tata McGraw Hill Publishing Company Limited, Special Indian Edition, 2007.
-  D. Sudhakar Samuel, “Logic Design: A Simplified Approach”, Sanguine Technical Publishers, Edition 1, 2006
 
Reference(s)
M Morris Mano and Michael D Ciletti, “Digital Design with Introduction to the Verilog HDL”, Pearson Education, Fifth Edition, Fifth Edition, 2015
John F. Wakerly, “Digital Design Principles and Practices”, Fourth Edition, Pearson Education, 3rd Ed, 2008.
Donald D Givone, “Digital Principles and Design”, Tata McGraw Hill Publishing Company Limited, 2003.