Course

Unit 1:

Concepts of VLSI Circuit Testing – Fault Modeling – Fault Collapsing – True Value Simulation – Fault Simulation – SCOAP Testability Measures – Combinational Circuit Test Generation – Roth’s D Algorithm – PODEM ATPG Algorithms.

Unit 2:

Sequential Circuit Test Generation – Simulation based ATPG – Test Set Compaction – NDetect ATPG – Design for Testability – Ad Hoc Techniques – Level-Sensitive Scan Design – Scan Architectures and Testing – Scan Design Rules – LFSR based Testing.

Unit 3:

Testable Logic Circuit Design – Logic BIST Architectures – Test Pattern Generation – Output Response Analysis – Test Stimulus Compression – Test Response Compaction – Memory BIST – RAM fault models – RAM Test Generation – Boundary Scan Architecture.

List of Experiments:

1. Algorithms for fault list reduction
2. Algorithms for test pattern generation
3. Algorithms for fault simulation
4. Algorithms for computing SCOAP Testability Measures
5. Algorithms for test power reduction
6. A script to automate T-max tool flow in Synopsys

• To introduce the fundamentals of VLSI testing and testability.
• To impart knowledge in the development of ATPG algorithms for testing.
• To explore the concepts of DFT and BIST.

At the end of the course, the student should be able to

• CO1: Ability to understand the concept of testing and testability in VLSI circuits.
• CO2: Ability to apply test pattern generation algorithms.
• CO3: Ability to analyze built-in-test concepts.
• CO4: Ability to design techniques for testability in scan-based architectures

Skills Acquired: Development of testing algorithms and testable scan architectures.

CO-PO Mapping:

1. Vishwani D. Agrawal and Michael L. Bushnell, Essentials of Electronic Testing for Digital Memory and Mixed Signal VLSI Circuits, Kluwer Academic Publishers, 2000.
2. Parag K. Lala, An Introduction to Logic Circuit Testing, Morgan &Claypool Publishers, 2009.
3. T. Wang, Cheng Wen Wu and Xiaoqing Wen, VLSI Test Principles and Architectures Design for Testability, First Edition, Morgan Kaufmann Publishers, 2006.
4. Miron Abramovici, Melvin A. Breuer and Arthur D. Friedman, Digital Systems Testing and Testable Design, Jaico Publishing House, 2001.