Course

Unit I

Programmable logic devices – PROM- PAL – PLA- CPLD – Gate arrays -MPGA – FPGA- Programming technologies – EPROM-EEPROM-FLASH-SRAM- FPGA fabric- Configurable logic block – LUT – Slice – SliceM – programmable interconnects – Input output blocks – keeper circuit – Xilinx 7 series architecture.

Unit II

FPGA Design flow and abstraction levels – Verilog design for synthesis-one hot encoding- Memory blocks- Block memory generator (BRAM/BROM)- single port memory- dual port memory- FIFO-distributed RAM-synthesis pitfalls-latch inference-static timing analysis-speed performance-timing constraints-clock management -clock buffers-clock tree routing

Unit III

Introduction to SoC design –Hard macros – multipliers –DSP block-hard core processors- interface circuits-– configuration chain – JTAG interface – Zynq7000

Learning Objectives

LO1    To introduce the internal architecture of programmable logic with focus on FPGA.

LO2    To provide knowledge in FPGA design flow at the architectural and system design.

LO3    To impart a good background in block-based design using standard system level tools. 

Course Outcomes

CO1    Ability to understand the structure of the fabric of programmable logic.

CO2    Ability to apply techniques for logic designing using field programmable devices.

CO3    Ability to analyse and comprehend FPGA design flow and related design, synthesis and
             timing issues.

CO4    Ability to evaluate system level architectures by integrating IP cores including softcore
             and hardcore processors. 

CO-PO Mapping

References

1. Amano, Hideharu, Principles and Structures of FPGAs, First Edition, Springer,
2. Readler, Blaine C., Verilog by example: a concise introduction for FPGA design. Full Arc Press,
3. Zainalabedin Navabi, Embedded Core Design with FPGAs, First Edition, McGraw Hill, 2008
4. Xilinx Inc, Vivado Design Suite User Guide, 2021