Course

Unit 1:

Review of HDL (Verilog) –Need for functional verification – Verification lifecycle and test planning – Testbench architectures: Directed & Constraint Random – Types of coverage: Code coverage – Functional coverage – SystemVerilog for design: data types, control flow, operators – Hierarchy, modules, and connectivity

Unit 2

SystemVerilog for Verification- Testbench components: tasks, functions, interfaces- Object-oriented features in SystemVerilog (classes, inheritance, polymorphism) – Constrained Random Verification-
Inter Process Communication: Threads, mailboxes and semaphores- Building verification environment with SystemVerilog

Unit 3

System Verilog Assertions – immediate assertions – concurrent assertions – Boolean assertions – Sequences – properties – implication operators – nested implications – Functional Coverage: covergroups, bins, cross coverage – Coverage closure strategies and reporting – Memory Design: Behavioural Modelling and Verification environment creation – UVM – Overview, Testbench Architecture, and Component Roles

• To develop a strong foundation in functional verification techniques used in ASIC/FPGA design
• To familiarize with SystemVerilog constructs for building testbenches and verification environments.
• To cultivate skills in assertion-based verification and functional coverage-driven testing

At the end of the course, the student should be able to

• CO1: Understand the fundamentals of functional verification and its methodologies.
• CO2: Design digital modules and corresponding testbenches using SystemVerilog
• CO3: Apply effective methodologies to develop effective verification environments
• CO4: Evaluate verification completeness using assertion-based techniques.

Skills Acquired: Creation of reusable testbenches using SystemVerilog; Verification planning and coverage closure; Application of functional coverage and assertion-based techniques.

CO-PO Mapping:

1. Chris Spear and Greg Tumbush: SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, 4th Edition, 2020.
2. Ashok B. Mehta, Introduction to SystemVerilog: Simulation and Testbench Design, Springer, 2021.
3. Janick Bergeron, Writing Testbenches Using SystemVerilog, 3rd Edition, Springer, 2016.
4. Ben Cohen, Srinivasan Venkataramanan, Ajeetha Kumari, Lisa Piper, SystemVerilog Assertions Handbook: For Design and Verification, 4th Edition, 2019.