Unit 1:
Introduction to VLSI Design Flow and HDLs –Verilog modeling styles – Gate Level – Structural – Dataflow –RTL Abstraction –RTL Design – Design and Synthesis of Logic Circuits with Verilog HDL.
Course Name | Digital Circuits and Systems |
Course Code | 25VL603 |
Program | M. Tech. in VLSI Design |
Credits | 3 |
Campus | Amritapuri, Coimbatore, Bengaluru, Chennai |
Introduction to VLSI Design Flow and HDLs –Verilog modeling styles – Gate Level – Structural – Dataflow –RTL Abstraction –RTL Design – Design and Synthesis of Logic Circuits with Verilog HDL.
Sequential Building Blocks – Latch, Flip-flops – Registers – Shift Registers and Digital Counters – Sequential multiplier – Finite State Machines (FSM)– Types of FSM – Design and Implementation – Capabilities and limitations of FSM –Digital Subsystem Design – FIFOs – Memories –Buffers
Fundamental mode model – Flow table – State reduction Races, Cycles and Hazards.
Case Study of Design and Modeling of a Simple Digital System – Datapath and Controller Design – Programmable Logic Devices – CPLD – FPGA – Verilog Design for FPGA Synthesis – Introduction to High Level Synthesis.
At the end of the course, the student should be able to
Skills Acquired: Design and modeling system-level architectures at the RTL abstraction level, and implementing the design with FPGA resources.
CO-PO Mapping:
CO/PO | PO 1 | PO 2 | PO 3 | PSO1 | PSO2 | PSO3 |
CO 1 | – | – | 3 | – | — | |
CO 2 | – | – | 3 | 3 | – | |
CO 3 | – | – | 3 | 3 | – | |
CO 4 | – | – | 3 | 3 | 3 |
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