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Course Detail

Course Name Multi Core Architectures
Course Code 25ES647
Program M. Tech. in Embedded Systems
Credits 3
Campus Bengaluru, Coimbatore

Syllabus

Syllabus

Review of Computer Design – Measuring performance Instruction level parallelism – Branch prediction techniques – Static & Dynamic scheduling Speculation – Limits of ILP. Thread-level parallelism, multi-issue, and multi-core processors Homogenous and Heterogenous multicore systems. Shared and Distributed memory -Transaction Memory issues Memory hierarchy design – Cache coherence, Memory wall problem – Advanced Cache Memory design – Virtual Memory, Storage Systems – Ware-house Scale Computers Power optimization- Dynamic Voltage Frequency Scaling – Multi-core architectures for embedded systems Fault Tolerant aspects for multi core systems- Programming environments for multi-core.

Text Books / References
  1. Peter S. Pacheco, “An Introduction to Parallel Programming,” Morgan Kauffman/Elsevier, 2011. 
  2. Yan Solihin, “Fundamentals of Parallel Multicore Architecture”, CRC Press, 2016. 
  3. Georgios Kornaros, “Multi-core Embedded Systems”, CRC Press, Taylor and Francis Group, First edition, 2019. 
  4. Victor Alessandrini, , “Shared Memory Application Programming, Concepts and Strategies in Multicore Application Programming”, 1stEdition,Morgan Kaufmann,2015. 
  5. Darryl Gove, “Multicore Application Programming for Windows, Linux, and Oracle Solaris”, Pearson, 2011. 

Objectives and Outcomes

Pre-requisite: Nil

Course Objectives:

  • To introduce computer performance metrics, instruction-level parallelism, and advanced processor design techniques.
  • To provide knowledge on multi-core architectures, memory hierarchy, cache coherence, and large-scale storage systems.
  • To develop an understanding of power optimization, fault tolerance, and programming environments for multi-core and embedded systems.

Course Outcomes:

CO1: Understand instruction level and thread level parallelism and branch prediction techniques. 
CO2: Develop static and dynamic scheduling algorithms. 
CO3: Analyse memory hierarchy design and cache coherency problem. 
CO4: Discuss concepts on multi-issue and multi-core processors with power optimization. 

CO-PO Mapping:

PO/PSO PO1 PO2 PO3 PSO1 PSO2
CO
CO1
CO2
CO3
CO4

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