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Mohankumar N.

Assistant Professor, Electronics and Communication Engineering, School of Engineering, Coimbatore

Qualification: M.Tech
n_mohankumar[at]cb[dot]amrita[dot]edu
Ph: +91 422 2685000 Ext. 5784
Mohankumar N's Google Scholar Profile
Research Interest: Biologically Inspired Computing Techniques, Biologicaly Inspired Computing, Design for Security, Digital IC Design, Digital Logic Design with HDL, Evolutionary Computing, Hardware Security & Trust, Micro & Nano Electronics

Bio

Mohankumar N. received his Master of Technology in Microelectronics and VLSI Design from National Institute of Technology Calicut (NITC) in 2008 and a Bachelor of Engineering in Electronics and Communication Engineering from Amrita Institute of Technology and Science (affiliated to Bharathiar University, Coimbatore) in 2004. Presently he is pursuing his research in the area of Hardware Security and Trust.

His research interests include Design for Security, Hardware Security & Trust, Digital IC Design, Biologically Inspired Computing Techniques. He has authored more than 30 technical publications in national and international journals and conferences. Presently he is serving as an Assistant Professor in the Department of Electronics and Communiaction Engineering, School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore, India.

In the capacity of Organizing Secretary he had organized five editions of flagship conference of Department of ECE – National Conference of Recent Trends in Communication, Computation and Signal Processing (RTCSP) under the aegis of IETE Coimbatore Center. He has also conducted several technical workshops for the benefit of the learning community. He is an Executive committee member of IETE Coimbatore Centre since 2004 and Member of Society for Failure Analysis.

 

Publications

Journal Article

Year : 2019

Random seeding LFSR-based TRNG for hardware security applications

Cite this Research Publication : S. R. Prasad, Siripagada, A., Selvaraj, S., and N Mohankumar, “Random seeding LFSR-based TRNG for hardware security applications”, Studies in Computational Intelligence, vol. 771, pp. 427-434, 2019.

Publisher : Springer Verlag,

Year : 2019

Wire load variation-based hardware trojan detection using machine learning techniques

Cite this Research Publication : S. N. Babu and Mohankumar, N., “Wire load variation-based hardware trojan detection using machine learning techniques”, Advances in Intelligent Systems and Computing, vol. 900, pp. 613-623, 2019.

Publisher : Advances in Intelligent Systems and Computing

Year : 2018

Virtual Instrumentation-Based Malicious Circuit Detection Using Weighted Average Voting

Cite this Research Publication : G. Aishwarya, Revalla, H., Shruthi, S., Ananth, V. S. P., and N Mohankumar, “Virtual Instrumentation-Based Malicious Circuit Detection Using Weighted Average Voting”, Lecture Notes in Electrical Engineering, vol. 471, pp. 423-431, 2018.

Publisher : Springer Verlag

Year : 2018

Delay-Based Reference Free Hardware Trojan Detection using Virtual Intelligence

Cite this Research Publication : K. S. Nandhini, Vallinayagam, S., Harshitha, H., Azad, V. A. Chandra Sh, and N Mohankumar, “Delay-Based Reference Free Hardware Trojan Detection using Virtual Intelligence”, Advances in Intelligent Systems and Computing, vol. 672, pp. 506-514, 2018.

Publisher : Springer Verlag

Year : 2018

CRC-Based Hardware Trojan Detection for Improved Hardware Security

Cite this Research Publication : N Mohankumar, Dr. Jayakumar M., and M. Devi, N., “CRC-Based Hardware Trojan Detection for Improved Hardware Security”, Lecture Notes in Electrical Engineering, vol. 471, pp. 381-389, 2018.

Publisher : Lecture Notes in Electrical Engineering

Year : 2018

HD-Sign: Hardware based Digital Signature Generation using True Random Number Generator

Cite this Research Publication : G. Anahita, Krishnapriya, K. P. M., R. Prasad, S., and N Mohankumar, “HD-Sign: Hardware based Digital Signature Generation using True Random Number Generator”, International Journal of Engineering and Technology(UAE), vol. 7, pp. 147-150, 2018.

Publisher : Science Publishing Corporation Inc

Year : 2018

HAPMAD: Hardware-based Authentication Platform for Malicious Activity Detection in Digital Circuits

Cite this Research Publication : V. R. R. Koneru, Teja, B. K., Reddy, K. D. B., GnanaSwaroop, M. V., Ramanidharan, B., and N Mohankumar, “HAPMAD: Hardware-based Authentication Platform for Malicious Activity Detection in Digital Circuits”, Advances in Intelligent Systems and Computing, vol. 672, pp. 608-617, 2018.

Publisher : Springer Verlag

Year : 2018

Design And Analysis of Analog TRNG Using Sample and Hold Circuit

Cite this Research Publication : B. Aksshaya, G V., M. L., S, N., T, V., and N Mohankumar, “Design And Analysis of Analog TRNG Using Sample and Hold Circuit”, International Journal of Engineering & Technology, vol. 7, pp. 69–73 doi = 10.14419/ijet.v7i3.8.15222, 2018.

Publisher : International Journal of Engineering & Technology.

Year : 2016

Improving the Classification Accuracy in Detecting Hardware Trojan in ALU Using PCA

Cite this Research Publication : N Mohankumar and NirmalaDevi, M., “Improving the Classification Accuracy in Detecting Hardware Trojan in ALU Using PCA”, Indian Journal of Science and Technology, vol. 9, no. 1, 2016.

Publisher : Indian Journal of Science and Technology

Year : 2012

Implementation of a Simplified Cultural-based Multi Objective Particle Swarm Optimization

Cite this Research Publication : A. Francis, .Kirthika, Y., Mohan, S., Nijil, M., A, E., P, S., and N Mohankumar, “Implementation of a Simplified Cultural-based Multi Objective Particle Swarm Optimization”, International Journal of Electronics Signals and Systems ( IJESS) , vol. 2, no. 2,3,4, 2012.

Publisher : IJESS

Year : 2011

Hardware Implementation of Genetic Algorithm based Digital Colour Image Watermarking

Cite this Research Publication : S. Sreejith, N Mohankumar, and M Devi, N., “Hardware Implementation of Genetic Algorithm based Digital Colour Image Watermarking”, Aceee International Journal on signal & Image processing, vol. 2, pp. 35-39, 2011.

Publisher : Academy Publishers

Year : 2010

Low Power Hardware Implementation of Color Image Watermarking for Real Time Application

Cite this Research Publication : S. S., N Mohankumar, and M Devi, N., “Low Power Hardware Implementation of Color Image Watermarking for Real Time Application”, Advances in Computational Sciences and Technology, vol. 3, no. 3, pp. 259-268, 2010.

Publisher : Advances in Computational Sciences and Technology

Year : 2009

Modeling and analysis of neuro–genetic hybrid system on FPGA

Cite this Research Publication : Dr. Nirmala Devi M., N Mohankumar, and Arumugam, S., “Modeling and analysis of neuro–genetic hybrid system on FPGA”, Elektronika ir Elektrotechnika (International Journal of Electrical and Electronics Engineering (JEEE)), vol. 96, pp. 69-74, 2009.

Publisher : Elektronika ir Elektrotechnika (International Journal of Electrical and Electronics Engineering (JEEE)

Year : 2009

Modelling and Analysis of Neuro-Genetic Hybrid System on FPGA

Cite this Research Publication : N Mohankumar, NirmalaDevi, M., and Arumugam, S., “Modelling and Analysis of Neuro-Genetic Hybrid System on FPGA”, International Journal of Electrical and Electronics Engineering (JEEE), no. 96, 2009.

Publisher : International Journal of Electrical and Electronics Engineering (JEEE)

Year : 2009

Design of Genetically Evolved Artificial Neural Network Using Enhanced Genetic Algorithm

Cite this Research Publication : N Mohankumar, NirmalaDevi, M., Karthick, M., Jayan, N., Nithya, R., Shobana, S., M Sundar, S., and Arumugam, S., “Design of Genetically Evolved Artificial Neural Network Using Enhanced Genetic Algorithm”, International Journal of Recent Trends in Engineering, vol. 1, no. 2, pp. 84-89, 2009.

Publisher : Academy Publishers, Finland

Conference Paper

Year : 2015

Malicious Circuit Detection for Improved Hardware Security

Cite this Research Publication : N. Devi M. R, ,, G. Sabari, A., Krishna, D. Ravi, Prasathe, A., Harish, K., and N Mohankumar, “Malicious Circuit Detection for Improved Hardware Security”, in The Third International Symposium on Security in Computing and Communications (SSCC’15), 2015.

Publisher : The Third International Symposium on Security in Computing and Communications (SSCC’15)

Year : 2014

Low Power Fault-Tolerant Reversible Full Adders

Cite this Research Publication : N Mohankumar, Ramesh, V. Ravikumar, Paramasivan, D., Ramya, H., and Raghavan, R., “Low Power Fault-Tolerant Reversible Full Adders”, in International Conference on Communication and Computing (ICC2014), 2014.

Publisher : International Conference on Communication and Computing (ICC2014)

Year : 2011

A compressed domain dual video watermarking for real-time applications

Cite this Research Publication : D. Badarinath, Scaria, A., Devi, M. N., and N Mohankumar, “A compressed domain dual video watermarking for real-time applications”, in Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011, Coimbatore, 2011.

Publisher : PACC

Year : 2011

Hardware implementation of svd based colour image watermarking in wavelet domain

Cite this Research Publication : A. Scaria, D. Nath, B., Dr. Nirmala Devi M., and N Mohankumar, “Hardware implementation of svd based colour image watermarking in wavelet domain”, in Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011, Coimbatore, 2011.

Publisher : PACC 2011

Year : 2009

Implementation of Artificial Neural Network Using Enhanced Genetic Algorithm

Publisher : Amrita Vishwa Vidyapeetham, Coimbatore

Conference Proceedings

Year : 2018

BHARKS: Built-in Hardware Authentication using Random Key Sequence

Cite this Research Publication : D. M. Reddy, Akshay, K. P., Giridhar, R., Karan, S. D., and N Mohankumar, “BHARKS: Built-in Hardware Authentication using Random Key Sequence”, 4th IEEE International Conference on Signal Processing, Computing and Control, ISPCC 2017, vol. 2017-January. Institute of Electrical and Electronics Engineers Inc., pp. 200-204, 2018.

Publisher : Institute of Electrical and Electronics Engineers Inc.

Year : 2014

Malicious Combinational Hardware Trojan Detection by Gate Level Characterization in 90nm technology

Cite this Research Publication : D. K. Karunakaran and N Mohankumar, “Malicious Combinational Hardware Trojan Detection by Gate Level Characterization in 90nm technology”, Fifth International Conference on Computing, Communications and Networking Technologies (ICCCNT). 2014.

Publisher : Fifth International Conference on Computing, Communications and Networking Technologies (ICCCNT)

Year : 2014

Evolving Reversible Fault-Tolerant Adder Architectures and their Power Estimation

Cite this Research Publication : N Mohankumar, “Evolving Reversible Fault-Tolerant Adder Architectures and their Power Estimation”, IEEE International Conference on Computing, Communication and Networking Technologies (ICCCNT 2014) to be held at Hefei. China, 2014.

Publisher : ICCCNT 2014

Year : 2014

Malicious Stuck-At Fault and Somersault Trojan Detection in Combinational Circuits using Power Analysis

Cite this Research Publication : N Mohankumar, “Malicious Stuck-At Fault and Somersault Trojan Detection in Combinational Circuits using Power Analysis”, Proceedings of 6th IRF International Conference. Chennai, India, 2014.

Publisher : Proceedings of 6th IRF International Conference

Year : 2014

Date Compression Techniques – A Survey

Cite this Research Publication : N Mohankumar, “Date Compression Techniques – A Survey”, Recent Trends In Communication and Signal processing,(RTCSP 2014), . Amrita Vishwa Vidyapeetham, Coimbatore, 2014.

Publisher : Recent Trends In Communication and Signal processing,(RTCSP 2014),

Year : 2013

Hardware Trojan Detection-A Survey

Cite this Research Publication : N Mohankumar, Periasamy, R., Sivaraj, P., and Thakur, A., “Hardware Trojan Detection-A Survey”, 4th National Conference on Recent Trends in Communication Computation and Signal Processing (RTCSP-2013). Department of ECE, Amrita Vishwa Vidyapeetham, CBE, Coimbature, pp. 99-102, 2013.

Publisher : Amrita Vishwa Vidyapeetham, Coimbatore

Year : 2011

VLSI Architecture for Compressed Domain Video Watermarking

Cite this Research Publication : N Mohankumar, M. Devi, N., D. Nath, B., and Scaria, A., “VLSI Architecture for Compressed Domain Video Watermarking”, Advances in Digital Image Processing and Information Technology. Springer Berlin Heidelberg, Berlin, Heidelberg, pp. 405-416 , 2011.

Publisher : Springer Berlin Heidelberg

Year : 2010

Simultaneous Evolution of Structure and Weights of Artificial Neural Networks using an improved PSO algorithm for Pattern Classification

Cite this Research Publication : N Mohankumar, “Simultaneous Evolution of Structure and Weights of Artificial Neural Networks using an improved PSO algorithm for Pattern Classification”, National Conference on Recent Trends In Communication and Signal processing,(RTCSP 2010). Amrita VishwaVidyapeetham,Coimbatore, 2010.

Publisher : Amrita VishwaVidyapeetham,Coimbatore

Year : 2010

Optimisation of Self Structuring Antenna using Feed Forward Neural Network with Improved Genetic aAlgorithm

Cite this Research Publication : N Mohankumar, “Optimisation of Self Structuring Antenna using Feed Forward Neural Network with Improved Genetic aAlgorithm”, National Conference on Recent Trends In Communication and Signal processing,(RTCSP 2010). Amrita VishwaVidyapeetham,Coimbatore, 2010.

Publisher : Amrita VishwaVidyapeetham,Coimbatore

Year : 2010

Low Power Implementation of Colour Image Watermarking for Real Time Application

Cite this Research Publication : N Mohankumar, “Low Power Implementation of Colour Image Watermarking for Real Time Application ”, National conference on Networking Paradigms & Cyber Security conducted as part of IETE South Zonal Seminar . 2010.

Publisher : National conference on Networking Paradigms Cyber Security conducted as part of IETE South Zonal Seminar

Year : 2010

Implementation of Fault Tolerant Feedforward Neural Networks in VLSI Hardware

Cite this Research Publication : N Mohankumar, “Implementation of Fault Tolerant Feedforward Neural Networks in VLSI Hardware”, 14th IEEE/VSI VLSI Design and Test Symposium (VDAT 2010), . Chandigarh, 2010.


Publisher : 14th IEEE/VSI VLSI Design and Test Symposium

Year : 2010

Evolving Artificial Neural Networks using PSO and GA

Cite this Research Publication : N Mohankumar, “Evolving Artificial Neural Networks using PSO and GA”, National Conference on Recent Trends In Communication and Signal processing,(RTCSP 2010), . Amrita VishwaVidyapeetham,Coimbatore, 2010.

Publisher : Amrita VishwaVidyapeetham,Coimbatore

Year : 2010

Artificial Neural Network Weight Evolution using PSO to solve n-bit parity Problem

Cite this Research Publication : N Mohankumar, “Artificial Neural Network Weight Evolution using PSO to solve n-bit parity Problem”, International conf. on Recent advancements in electrical Sciences (ICRAES’10). Tiruchengode, 2010.

Publisher : ICRAES’10

Year : 2009

Improved Eye locating Algorithm for Driver Fatigue Monitoring

Cite this Research Publication : N Mohankumar, “Improved Eye locating Algorithm for Driver Fatigue Monitoring”, National Conference on Recent Trends in Communication and Signal Processing (RTCSP09). Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore ,Tamil Nadu, 2009.

Publisher : Amrita School of Engineering, Amrita Vishwa Vidyapeetham,

Year : 2009

Implementation of Artificial Neural Network Using Enhanced Genetic Algorithm

Publisher : Amrita Vishwa Vidyapeetham, Coimbatore

Year : 2009

Implementation and Simulation of ANN with NN and GA

Cite this Research Publication : N Mohankumar, “Implementation and Simulation of ANN with NN and GA”, 3rd International Conference on Intelligent Systems & Network (IISN-2009). 2009.

Publisher : 3rd International Conference on Intelligent Systems Network (IISN-2009)

Year : 2009

A Neuro-Hardware for Epilepsy Classification using Modified Genetic Algorithm

Cite this Research Publication : M. Ganesan, N. Kumar, M., and M. Nirmala Devi, “A Neuro-Hardware for Epilepsy classification using Modified Genetic Algorithm”, International conference on Electronic Design and Signal Processing ICEDSP09. MIT, Manipal , 2009.

Publisher : MIT, Manipal

Year : 2009

Efficient Parallel CRC Architecture Implementation Using VSP Techniques

Cite this Research Publication : N Mohankumar, “Efficient Parallel CRC Architecture Implementation Using VSP Techniques”, National Conference on Recent Trends in Communication and Signal Processing (RTCSP09). Amrita Vishwa Vidyapeetham, Coimbatore ,Tamil Nadu, 2009.

Publisher : National Conference on Recent Trends in Communication and Signal Processing (RTCSP09)

Year : 2009

Design of Artificial Neural Network with NN, EGA and its FPGA implementation

Cite this Research Publication : N Mohankumar, “Design of Artificial Neural Network with NN, EGA and its FPGA implementation”, National Conference on Embedded Systems EMCON – ’09 . Kalaslingam University Tamilnadu, 2009.

Publisher : Kalaslingam University Tamilnadu

Year : 2008

FPGA Realization of Activation Function for Artificial Neural Networks

Cite this Research Publication : Va Saichand, Dr. Nirmala Devi M., Arumugam, Sc, and N Mohankumar, “FPGA Realization of Activation Function for Artificial Neural Networks”, IEEE 8th International Conference on Intelligent Systems Design and Applications, ISDA 2008, vol. 3. IEEE, Taiwan, pp. 159-164, 2008.

Publisher : IEEE

Year : 2008

A Modified Genetic Algorithm for Evolution of Neural Network in Designing an Evolutionary Neuro-Hardware

Cite this Research Publication : N Mohankumar, Bhuvan, Bb, NirmalaDevi, Mc, and Arumuga, Sd, “A Modified Genetic Algorithm for Evolution of Neural Network in Designing an Evolutionary Neuro-Hardware”, Proceedings of the 2008 International Conference on Genetic and Evolutionary Methods, GEM 2008. Las Vegas, NV, pp. 108-111, 2008.

Publisher : Proceedings of the 2008 International Conference on Genetic and Evolutionary Methods, GEM 2008

Education
  • Pursuing: Ph. D. in Hardware Security and Trust
    Amrita Vishwa Vidyapeetham
  • 2008: M. Tech. in Microelectronics and VLSI Design
    NIT Calicut
Professional Experience
Year Affiliation
January 1, 2011 – Till Present Assistant Professor (Sr. Gr.), Amrita Vishwa Vidyapeetham
Domain : Teaching, Research and Projects, Dept. Administration
July 1, 2010 – December 31, 2010 Assistant Professor (Or. Gr.), Amrita Vishwa Vidyapeetham
Domain : Teaching, Research, Dept. Administration
July 1, 2004 – June 30, 2010 Lecturer, Amrita Vishwa Vidyapeetham
Domain : Teaching
Academic Responsibilities
Position Class / Batch Responsibility
Class Adviser 2017 – 21 Mentoring and Counseling
Undergraduate Courses Handled
  1. Electronics Engineering
  2. Neural Networks
  3. VLSI Technology
  4. VLSI Design
  5. Soft Computing
  6. Hardware Design Lab
  7. VLSI System Design
  8. Electronic Circuits
  9. Introduction to Soft Computing
Post-Graduate / Ph. D. Courses Handled
  1. Digital System Design (Embedded Systems and Power Electronics)
  2. CMOS Digital Integrated Circuits (VLSI Design)
  3. FPGA based System Design(Embedded Systems and Power Electronics)
  4. Reconfigurable Computing(VLSI Design)
  5. Hardware Software Co-design for Automotive Applications( Automotive Electronics)
Participation in Faculty Development / STTP / Workshops /Conferences
SNo Title Organization Period Outcome
1 STTP course on introduction to digital signal Processing and its applications November 22 to December 3, 2004
2 Smart Sensors Technology and Appliations Amrita Banglore April 2, 2005
3 One day workshop on Wavelets and Fuzzy Mathematics NITC January 20, 2007
4 Microsoft Uaer Group- Critical Thinking Workshop Microsoft March 23, 2008
5 One day Course on Nanotechnology Jul 13, 2009
6 Mission10X Workshop for High Impact Teaching Wipro December 20 – 24, 2010
7 Two day workshop on VLSI Design Techniques using Xilinx PPG and Correel November 3 – 4, 2011 Tool flow about Xilinx
8 Matlab and simulink for Engineering Education Mathworks March 3, 2013
9 Emerging Perspectives in Nanoelectronics R & D September 19, 2014 Understanding about nanoelectronic advancements
10 Emerging Perspectives in Nanoelectronics and R & D Amrita September 19, 2014
11 18th International Symposium on VLSI Design and Test VLSI Society of India July 16 – 18, 2014
12 Faculty Development Program on IC design using Mento Graphics Tool Coreel January 29 – 30, 2015
13 National Instruments Academic Conclave National Instruments and ICTACT
14 SPRINGER Author Workshop SPRINGER March 18, 2016
15 One day workshop on Cloud Based Machine Learning for IoT device PantechProEd September 2, 2018 Understanding about Cloud connectivity
Organizing Faculty Development / STTP / Workshops /Conferences
SNo Title Organization Period Outcome
1 IETE sponsored four day workshop on Analog Circuit Design and Signal Processing IETE, AMRITA 14th July, 2008 to 17th July, 2008 Technical Skill development
2 IETE Sponsored Two Day workshop on VLSI Front end Design Tools IETE, AMRITA 30, September, 2009
to 1st October, 2009
Technical Skill development
3 One day workshop on Microcontroller based Robotics CISCOE 11th October, 2009 Technical Skill development
4 One day workshop on Embedded Wireless Robotics CISCOE 26th august, 2009 Technical Skill development
5 First National Conference on Recent Trends in Communication, Computation and Signal Processing (RTCSP 2009) AMRITA 7th April 2009 Technical Skill development
6 Teaching and Learning VLSI Design – A Simulation based approach IETE, AMRITA 1st December to 4th 2010 Technical Skill development
7 IETE sponsored Three day Workshop on PIC Microcontrollers IETE, AMRITA 19th to 21st July, 2010 Technical Skill development
8 Brainracker 2010 – Mental Agility quiz 23rd April, 2010 Technical competence improvement
9 IETE South Zonal Seminar IETE 13th and 14th August 2010. Technical Skill development
10 Second National Conference on Recent Trends in Communication, Computation and Signal Processing (RTCSP 2010) AMRITA 26th to 27th March 2010 Technical Skill development
11 One day workshop on Electronic Design and Automation Tools IETE, AMRITA 23rd January, 2011 Students were able to use EDA tools for VLSI
12  IETE sponsored workshop on VLSI Simulation and synthesis Tools IETE, AMRITA 10 and 11 May, 2011 Students were able to use simulation tools
Two week ISTE Workshop on Basic Electronics ISTE and IITB 28th June to 8th July 2011 Knowledge Sharing on Basic Electronics
13 Third National Conference on Recent Trends in Communication, Computation and Signal Processing (RTCSP 2010) AMRITA 1st and 2nd March 2011 Technical Skill development
14 International Conference on Communication Technology and System Design (ICCTSD) AMRITA December 7 – 9, 2011. Technical Skill development
15 National Workshop on Advances in Signal and Image Processing IETE, AMRITA  30th May, 2012 to 2nd June, 2012 Technical Skill development
16 One day Workshop on Android based Logic Circuit Simulation Tools using AAKASH-II AMRITA 16th November, 2012 Students were exposed to the usage of Android based ICT simulation tools
17 PARIGNAN 2013 – IETE Students Day IETE 1st February, 2013 Technical competence improvement
18 Fourth National Conference on Recent Trends in Communication, Computation and Signal Processing (RTCSP 2010) AMRITA 10th April, 2013. Technical Skill development
19 One day workshop on VLSI- The past and the present with today’s emerging challenges of security AMRITA 8th Jan, 2014 Technical Skill development
20 Two Day IETE Workshop on “Instrumentation in Petrochemical Industries AMRITA August 21 and 22, 2014 Technical Skill development
21 IETE Foundation Day &SardarVallabhai Patel Birth anniversary Quiz – “Hi Q – A Quiz Battle” IETE 31st October, 2014 Technical competence improvement
22 UG Projects Evaluation, Assessment and Implementation AMRITA 8th August, 2014. Technical Skill development
23 Progress in Hardware Security AMRITA 23rd August, 2014 Technical Skill development
24 Two Day National symposium on Green Electronics AMRITA 12th and 13 December 2014 Technical Skill development
25 Fifth National Conference on Recent Trends in Communication, Computation and Signal Processing (RTCSP 2014) AMRITA 26 – 27, February , 2014 Technical Skill development
26 Connected Cars and IoT AMRITA 15th September, 2015 Technical Skill development
27 2nd IETE Student Forum National Congress 2015 AMRITA 13, 14 February, 2015 Technical Skill development
28 Higher Studies in US: MS and Ahead AMRITA 12 January , 2015 Idea on Higher studies overseas
29 Recent Advances in Automotive Electronics AMRITA 18, April 2015 Technical Skill development
30 Hardware Security Testing and Communication Security AMRITA 8th June 2016 Technical Skill development
31 Basic Electronics-A practical based approach AMRITA 15th oct, 2016 Technical Skill development
32 Two Training Program on CADENCE EDA Tool AMRITA 27th 28th July 2018 Technical Skill development
Academic Research – PG Projects
SNo Name of the Scholar Programme Specialization Duration Status
1 SK.Kamruddin Khan VLSI Design VLSI Architecture 2008-2009 Completed
2 Siddharth Shelly VLSI Design VLSI Architecture 2008-2009 Completed
3 Sreejith S VLSI Design Digital IC Design for image Processing 2009-2010 Completed
4 D. Badrinath VLSI Design Digital IC Design for Video Processing 2010-2011 Completed
5 VipinNambiar VLSI Design VLSI Architecture 2011-2012 Completed
6 Dinesh Kumar K VLSI Design Hardware Security 2013-2014 Completed
7 Sreenath N VLSI Design Hardware Security 2015-2016 Completed
8 Mangkeshwar. M. VLSI Design VLSI Physical Design 2015-2016 Completed
9 SakkthiSaranya .A.C VLSI Design Hardware Security 2015-2016 Completed
10 Palamandala Sindhu VLSI Design RF Chirp Digital Radar Implementation if FPGA 2016-2017 Completed
11 AnuradhaShankar VLSI Design Low Power Chip Design 2016-2017 Completed
12 SiripragadaAnirudh VLSI Design Design for Security 2017-2018 Completed
13 Suresh N VLSI Design Design for Security 2017-2018 Completed
14 SreshmaAmbadi VLSI Design Design for Security 2018-2019 Ongoing
15 Jaxin Baby VLSI Design Design for Security 2018-2019 Ongoing
Sponsored Research
SNo Title Agency Amount Duration Status
1. Hardware Trojan Detection & Consistence based Diagnosis Scientific Analysis Group (SAG) , DRDO 24 Lakhs 2015-2017 Completed
Research Laboratories – Developed / Associated
Location Name and Year Sponsoring Agency Domain No. of Publications No. of Funded projects No. of PG / PhDs
D-301, AB-II Hardware Security Lab (2010) DRDO VLSI Design and Security 9 1 PG:10
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