Qualification: 
M.Tech
n_mohankumar@cb.amrita.edu

Mohankumar N. currently serves as Assistant Professor at Department of Electronics and Communication Engineering, School of Engineering, Coimbatore Campus. His areas of research include Digital IC Design, Micro & Nano Electronics, Digital Logic Design with HDL, Evolutionary Computing and Biologically Inspired Computing.

Publications

Publication Type: Journal Article

Year of Conference Title

2019

S. R. Prasad, Siripagada, A., Selvaraj, S., and N Mohankumar, “Random seeding LFSR-based TRNG for hardware security applications”, Studies in Computational Intelligence, vol. 771, pp. 427-434, 2019.[Abstract]


Rapid developments in the field of cryptography and hardware security have increased the need for random number generators which are not only of low-complexity but are also secure to the point of being undeterminable. A random number generator is a part of most security systems, so it should be simple and area efficient. Many modern-day pseudorandom number generators (PRNGs) make use of linear feedback shift registers (LFSRs). Though these PRNGs are of low complexity, they fall short when it comes to being secure since they are not truly random in nature. Thus, in this chapter we propose a random seeding LFSR-based truly random number generator (TRNG) which is not only of low complexity, like the aforementioned PRNGs, but is also ‘truly random’ in nature. Our proposed design generates an n-bit truly random number sequence that can be used for a variety of hardware security based applications. Based on our proposed n-bit TRNG design, we illustrate an example which generates 16-bit truly random sequences, and a detailed analysis is shown based on National Institute of Standards and Technology (NIST) tests to highlight its randomness

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2018

B. Aksshaya, G V., M. L., S, N., T, V., and N Mohankumar, “Design And Analysis of Analog TRNG Using Sample and Hold Circuit”, International Journal of Engineering & Technology, vol. 7, pp. 69–73 doi = 10.14419/ijet.v7i3.8.15222, 2018.[Abstract]


Implementation of analog True random number generators is inevitable in almost all the security applications and encryption protocols nowadays. Although many digital True Random Number Generators are available, we proposed a method of random number generation using analog module of mixed signals. In actual fact generation of True Random Numbers is by utilizing the sample and hold circuit which is controlled by another random clock source, and a post processing circuit for generation of unpredictable binary sequence of numbers. The primary input source is an analog signal, essentially highly random noise from the external environment. The high unpredictability, less resource and simple circuit design are some highlights of the proposed work. Finally, the randomness is evaluated using NIST test suites and results are plotted and analyzed.

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2018

G. Anahita, Krishnapriya, K. P. M., R. Prasad, S., and N Mohankumar, “HD-Sign: Hardware based Digital Signature Generation using True Random Number Generator”, International Journal of Engineering and Technology(UAE), vol. 7, pp. 147-150, 2018.[Abstract]


With the recent advancements in the field of computing, a fair share of easier and safer practices to exchange and share information between multiple parties have propped up. While some of these are improvisations, a few such as the Digital Signatures, have fast replaced conventional signing practices. It's wide use and acceptance in the industry as well as officially, has necessitated higher security to protect data integrity and privacy. These digital Signatures are generated on the basis of various schemes that are designed to accommodate efficiency, crypto security and algorithmic complexity. This paper proposes an alternate method named HD-SIGN for generating these digital signatures in accordance with Secure Hash Function and 512-bit SRNN cryptographic algorithm. With the aid of a TRNG module, a modification to produce a large number with two prime factors and a set of natural numbers in a pair of public and private keys has been incorporated. The LSFR based TRNG module which helps maintain the "True Randomness? of any generated number has been used for this purpose. Further, the random nature of the generated sequence to be used in the digital signature, has been tested with the help of standard NIST tests. The Hamming distance has also been analyzed as a security metric for the proposal, implying the degree of unpre-dictability of the generated true random sequences.

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2018

K. S. Nandhini, Vallinayagam, S., Harshitha, H., Azad, V. A. Chandra Sh, and N Mohankumar, “Delay-Based Reference Free Hardware Trojan Detection using Virtual Intelligence”, Advances in Intelligent Systems and Computing, vol. 672, pp. 506-514, 2018.[Abstract]


Virtual instrumentation is a powerful tool that has been largely left unexplored in the domain of hardware security. It facilitates creation of automated tests to detect the presence of Trojans in a circuit thereby reducing the chance of human errors and the time required for testing. The presence of a stealthy Trojan in large VLSI circuits could lead to leakage of confidential information even in high-security applications such as defense equipment. Here, we propose the usage of virtual instrumentation to detect the presence of a delay-based Trojan in a circuit. Our results confirm that VI-based systems provide a cheap, self-sufficient, easy-to-use interface, and flexible scheme which can be easily modified to accommodate any VLSI circuit. This can also be used in other detection techniques without the need for use of complex systems.

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2018

V. R. R. Koneru, Teja, B. K., Reddy, K. D. B., GnanaSwaroop, M. V., Ramanidharan, B., and N Mohankumar, “HAPMAD: Hardware-based Authentication Platform for Malicious Activity Detection in Digital Circuits”, Advances in Intelligent Systems and Computing, vol. 672, pp. 608-617, 2018.[Abstract]


Hardware Trojans pose a major threat to the security of many industries and government agencies. This paper proposes a non-destructive method for detection of Hardware Trojans named HAPMAD—Hardware-Based Authentication Platform for Malicious Activity Detection in Digital Circuits using a combination of enhanced voting algorithm and hybrid voting algorithm (power and time analysis). Detecting a hardware Trojan is a cumbersome task. In most cases, the hardware Trojan can be detected only by activating it or by magnifying the Trojan activity. The detection efficiency using enhanced weighed voting is promising but in the case of Trojan circuits where there is no change in the output of the circuit; enhanced weighed voting algorithm fails to detect the Trojans effectively. Therefore, a two-phased voting algorithm is performed to increase the detection efficiency. ISCAS ‘85 Benchmark circuits were used to test the efficiency of the proposed technique. © Springer Nature Singapore Pte Ltd. 2018.

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2018

N Mohankumar, Dr. Jayakumar M., and M. Devi, N., “CRC-Based Hardware Trojan Detection for Improved Hardware Security”, Lecture Notes in Electrical Engineering, vol. 471, pp. 381-389, 2018.[Abstract]


Several methodologies aim at tackling the issue of Hardware Trojans through the help of a “Golden Reference”, which is not always available; thereby arises the need for an efficient method without a Golden Reference. This work involves the detection of Hardware Trojan in a circuit using an improved voting algorithm employing CRC. Two modifications to a conventional voting algorithm are proposed in this chapter along with CRC to improve the detection efficiency. This logic-based detection procedure avoids the requirements of complex pre-processing procedures like segmentation, fingerprinting, thermal imaging, etc., The following proposed modifications (i) incapacitates the bias toward 1s and incorporating CRC for comparison of bit streams and (ii) equal weight of 1 is given as initial weight to all CUTs, which gives better results in voting algorithm. Detection accuracy is found to be around 95.27% based on the detailed analysis with infected and non-infected ISCAS’85 and ISCAS’89 circuits.

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2018

G. Aishwarya, Revalla, H., Shruthi, S., Ananth, V. S. P., and N Mohankumar, “Virtual Instrumentation-Based Malicious Circuit Detection Using Weighted Average Voting”, Lecture Notes in Electrical Engineering, vol. 471, pp. 423-431, 2018.[Abstract]


The security of an entire system can be breached owing to a Hardware Trojan attack on the chip. Though many techniques are available to detect the presence of a Trojan, most of them need a reference circuit or require sophisticated Electronic Design Automation tools. Moreover, golden reference circuits are not always available. However, with the usage of average-weighted voting algorithm, the use of reference circuits can be avoided to identify the infected circuits. The automation of the detection test can be achieved by the use of virtual instrumentation. The proposed method ensures the functionality of the circuit. The results obtained assert that this detection system is modular, flexible, and also supports the integrations to accommodate any VLSI circuit off the shelf. This eliminates the use of any complex systems and can act as a standalone Trojan detection system

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2016

N Mohankumar and NirmalaDevi, M., “Improving the Classification Accuracy in Detecting Hardware Trojan in ALU Using PCA”, Indian Journal of Science and Technology, vol. 9, no. 1, 2016.[Abstract]


Present day electronic chips are outsourced by the manufacturer and done by third-parties. Such practices are widely
prevalent as it works out to be more profitable in terms of cost and effort to complete these processes offshore in
VLSI foundries. This comes with a potential risk of compromised security due to hardware Trojans. There are existing
methodologies which aim at tacking the issue of Hardware Trojans by detecting it. Hardware Trojan detection by
decomposing the design into blocks to detect combinational Trojan and Sequential Trojan is proposed in this paper. By
comparing the leakage and total power values consumed by both the design i.e. with and without the presence of the
hardware Trojans, we can identify the presence of the hardware Trojans. Moreover if the measurement noise gets high it
masks or hides the effect of the variation in power profile, which leads to a wrong decision. So by taking the measurement
noise under consideration the classification is effectively done for magnifying the differences by using Principle Component
Analysis approach and tested with 8, 16 and 32 bit ALU designs.

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2012

A. Francis, .Kirthika, Y., Mohan, S., Nijil, M., A, E., P, S., and N Mohankumar, “Implementation of a Simplified Cultural-based Multi Objective Particle Swarm Optimization”, International Journal of Electronics Signals and Systems ( IJESS) , vol. 2, no. 2,3,4, 2012.[Abstract]


— This paper presents a simplified Cultural based Multi-Objective Particle Swarm Optimization (MOPSO) algorithm. In this algorithm we modify momentum and global acceleration components of the conventional MOPSO algorithm. The algorithm has been tested on common benchmark functions. Its performance has been compared with other algorithms, using standard test metrics. The results show that the cultural based MOPSO is more efficient and robust.

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2011

S. Sreejith, N Mohankumar, and M Devi, N., “Hardware Implementation of Genetic Algorithm based Digital Colour Image Watermarking”, Aceee International Journal on signal & Image processing, vol. 2, pp. 35-39, 2011.[Abstract]


The objective of this work is to develop a hardware-based watermarking system to identify the device using which the photograph was taken. The watermark chip will be fit in any electronic component that acquires the images, which are then watermarked in real time while capturing along with separate key. Watermarking is the process of embedding the watermark, in which a watermark is inserted in to a host image while extracting the watermark the watermark is pulled out of the image.

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2010

S. S., N Mohankumar, and M Devi, N., “Low Power Hardware Implementation of Color Image Watermarking for Real Time Application”, Advances in Computational Sciences and Technology, vol. 3, no. 3, pp. 259-268, 2010.[Abstract]


The objective of this work is to develop a hardware-based watermarking system to identify the device using which the photograph was taken. The watermark chip will be fit in any electronic component that acquires the images, which are then watermarked in real time while capturing along with separate key. Watermarking is the process of embedding the watermark, in which a watermark is inserted in to a host image while extracting; the watermark is pulled out of the image. The ultimate objective of the research presented in this paper is to develop low-power, high-performance, real-time, reliable and secure watermarking systems, which can be achieved through hardware implementations. In this paper the development of a very large scale integration (VLSI) architecture for a high-performance watermarking chip that can perform invisible color image watermarking using genetic algorithm is discussed and the color image watermarking using LFSR unit is verified and synthesized. The prototyped VLSI implementation of watermarking is simulated with ModelSim and synthesized in Altera Cyclone II Family.

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2009

N Mohankumar, NirmalaDevi, M., and Arumugam, S., “Modelling and Analysis of Neuro-Genetic Hybrid System on FPGA”, International Journal of Electrical and Electronics Engineering (JEEE), no. 96, 2009.

2009

N Mohankumar, NirmalaDevi, M., Karthick, M., Jayan, N., Nithya, R., Shobana, S., M Sundar, S., and Arumugam, S., “Design of Genetically Evolved Artificial Neural Network Using Enhanced Genetic Algorithm”, International Journal of Recent Trends in Engineering, vol. 1, no. 2, pp. 84-89, 2009.[Abstract]


Neural Network (ANN) whose weights are genetically evolved using the proposed Enhanced Genetic Algorithm (EGA), thereby obtaining optimal weight set. The performance is analysed by fitness function based ranking. The ability of learning may depend on many factors like the number of neurons in the hidden layer, number of training input patterns and the type of activation function used. By varying each parameter, the performance of the proposed EGA algorithm is compared with normal NN training.

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2009

Dr. Nirmala Devi M., N Mohankumar, and Arumugam, S., “Modeling and analysis of neuro–genetic hybrid system on FPGA”, Elektronika ir Elektrotechnika (International Journal of Electrical and Electronics Engineering (JEEE)), vol. 96, pp. 69-74, 2009.[Abstract]


Simultaneous evolution of the architecture and adaptation of weights of an Artificial Neural Network is executed using Genetic Algorithm (GA) to overcome the local minima problem. Absence of learning unit simplifies the Very Large Scale Integration (VLSI) realization of evolved Neural Network (NN). Potential of the Neurohardware is tested on two benchmark circuits; Eight-bit even Parity function and nine-bit Character Recognition. Binary input facilitates the use of comparators instead of multipliers in the hidden layer neuron, reducing the hardware complexity. While evolving the parity function using GA, the number of hidden layer neuron is reduced to half, which in turn reduces the silicon area appreciably. Character Recognition Network converges faster with acceptable error. Simulated results ensure that the designed Neuro-Genetic Hybrid System is not only fast and accurate but also hardware friendly.

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Publication Type: Conference Proceedings

Year of Conference Title

2018

D. M. Reddy, Akshay, K. P., Giridhar, R., Karan, S. D., and N Mohankumar, “BHARKS: Built-in Hardware Authentication using Random Key Sequence”, 4th IEEE International Conference on Signal Processing, Computing and Control, ISPCC 2017, vol. 2017-January. Institute of Electrical and Electronics Engineers Inc., pp. 200-204, 2018.[Abstract]


In today's world, as the demand for IC production grows exponentially, testing and validation of all the manufactured chips becomes impossible. Therefore, in the proposed method, we have developed a technique for embedding unique signatures with minimalistic hardware or area overhead while preserving the intended functionality. To achieve this, three 'levels' of security are provided. First, circuit specific information is derived and used for signature generation. Second, the generated signature is hashed, obfuscating the logic reverse engineering process and finally a bit sequence from a Pseudo-Random Number Generator (PRNG) to make it unfeasibly difficult for the attacker to decode the signature

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2014

N Mohankumar, “Date Compression Techniques – A Survey”, Recent Trends In Communication and Signal processing,(RTCSP 2014), . Amrita Vishwa Vidyapeetham, Coimbatore, 2014.

2014

N Mohankumar, “Hardware Trojan Detection-A Survey”, Proc. of 5th National Conference on Recent Trends In Communication and Signal processing,(RTCSP 2014). Amrita Vishwa Vidyapeetham, Coimbatore, 2014.

2014

N Mohankumar, “Malicious Stuck-At Fault and Somersault Trojan Detection in Combinational Circuits using Power Analysis”, Proceedings of 6th IRF International Conference. Chennai, India, 2014.

2014

N Mohankumar, “Evolving Reversible Fault-Tolerant Adder Architectures and their Power Estimation”, IEEE International Conference on Computing, Communication and Networking Technologies (ICCCNT 2014) to be held at Hefei. China, 2014.

2014

D. K. Karunakaran and N Mohankumar, “Malicious Combinational Hardware Trojan Detection by Gate Level Characterization in 90nm technology”, Fifth International Conference on Computing, Communications and Networking Technologies (ICCCNT). 2014.[Abstract]


Globalization of Integrated Circuits (IC's) in semiconductor industries has made them vulnerable to intentional alterations of the design. These intentional alterations to a design are called Hardware Trojans (HT's). Since many of the designs are outsourced for its fabrication, there is a lot of chance for altering its functionality. It is very important to detect these Trojans as it may raise serious concern about hardware trust, especially in the field of military and security applications. This paper considers the detection of combinational trojans using Gate Level Characterization (GLC) and is based on the measurement of side-channel parameters, especially leakage power. The leakage power for an entire circuit is being calculated for each input vector. The obtained measurements are formulated as linear equations in Linear Programming (LP) and are solved using LP solver.

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2013

N Mohankumar, Periasamy, R., Sivaraj, P., and Thakur, A., “Hardware Trojan Detection-A Survey”, 4th National Conference on Recent Trends in Communication Computation and Signal Processing (RTCSP-2013). Department of ECE, Amrita Vishwa Vidyapeetham, CBE, Coimbature, pp. 99-102, 2013.[Abstract]


Today's integrated circuits are vulnerable to hardware Trojans, which are malicious alterations to the circuit, either during design or fabrication. This article presents a classification of hardware Trojans and a survey of published techniques for Trojan detection. More »»

2011

N Mohankumar, M. Devi, N., D. Nath, B., and Scaria, A., “VLSI Architecture for Compressed Domain Video Watermarking”, Advances in Digital Image Processing and Information Technology. Springer Berlin Heidelberg, Berlin, Heidelberg, pp. 405-416 , 2011.[Abstract]


Digital watermarking has become very important for protecting the authenticity of multimedia objects as they become easier to copy, exchange, and modify due to the large diffusion of powerful personal computers. The video has been utilized in a variety of applications such as video editing, Internet video distribution, wireless video communications etc. Some of these applications are likely to get great benefit from video watermarking technology. Main objective of this research is to design robust perceptual video watermarking targeted at achieving better performance and reliability. Due to its robust nature, Discrete Cosine Transform (DCT) watermarking was chosen in this work to accomplish video copyright protection. The watermark is inserted in the video stream during compression, resulting in an optimized compression/watermarking algorithm and system.

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2010

N Mohankumar, “Low Power Implementation of Colour Image Watermarking for Real Time Application ”, National conference on Networking Paradigms & Cyber Security conducted as part of IETE South Zonal Seminar . 2010.

2010

N Mohankumar, “Optimisation of Self Structuring Antenna using Feed Forward Neural Network with Improved Genetic aAlgorithm”, National Conference on Recent Trends In Communication and Signal processing,(RTCSP 2010). Amrita VishwaVidyapeetham,Coimbatore, 2010.

2010

N Mohankumar, “Evolving Artificial Neural Networks using PSO and GA”, National Conference on Recent Trends In Communication and Signal processing,(RTCSP 2010), . Amrita VishwaVidyapeetham,Coimbatore, 2010.

2010

N Mohankumar, “Simultaneous Evolution of Structure and Weights of Artificial Neural Networks using an improved PSO algorithm for Pattern Classification”, National Conference on Recent Trends In Communication and Signal processing,(RTCSP 2010). Amrita VishwaVidyapeetham,Coimbatore, 2010.

2010

N Mohankumar, “Implementation of Fault Tolerant Feedforward Neural Networks in VLSI Hardware”, 14th IEEE/VSI VLSI Design and Test Symposium (VDAT 2010), . Chandigarh, 2010.

2010

N Mohankumar, “Artificial Neural Network Weight Evolution using PSO to solve n-bit parity Problem”, International conf. on Recent advancements in electrical Sciences (ICRAES’10). Tiruchengode, 2010.

2009

N Mohankumar, “Improved Eye locating Algorithm for Driver Fatigue Monitoring”, National Conference on Recent Trends in Communication and Signal Processing (RTCSP09). Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore ,Tamil Nadu, 2009.

2009

N Mohankumar, “Efficient Parallel CRC Architecture Implementation Using VSP Techniques”, National Conference on Recent Trends in Communication and Signal Processing (RTCSP09). Amrita Vishwa Vidyapeetham, Coimbatore ,Tamil Nadu, 2009.

2009

N Mohankumar, “Implementation of Artificial Neural Network Using Enhanced Genetic Algorithm”, National Conference on Recent Trends in Communication and Signal Processing (RTCSP09), . Amrita Vishwa Vidyapeetham, Coimbatore ,Tamil Nadu, 2009.

2009

N Mohankumar, “Design of Artificial Neural Network with NN, EGA and its FPGA implementation”, National Conference on Embedded Systems EMCON – ’09 . Kalaslingam University Tamilnadu, 2009.

2009

N Mohankumar, “Implementation and Simulation of ANN with NN and GA”, 3rd International Conference on Intelligent Systems & Network (IISN-2009). 2009.

2008

N Mohankumar, “A Neuro-Hardware for Epilepsy Classification using Modified Genetic Algorithm”, International conf. on Electronic Design and Signal processing '08(ICEDSP’08). 2008.

2008

Va Saichand, Dr. Nirmala Devi M., Arumugam, Sc, and N Mohankumar, “FPGA Realization of Activation Function for Artificial Neural Networks”, IEEE 8th International Conference on Intelligent Systems Design and Applications, ISDA 2008, vol. 3. IEEE, Taiwan, pp. 159-164, 2008.[Abstract]


Implementation of Artificial Neural network (ANN) in hardware is needed to fully utilize the inherent parallelism. Presented work focuses on the configuration of Field-Programmable Gate Array (FPGA) to realize the activation function utilized in ANN. The computation of a nonlinear activation function (AF) is one of the factors that constraint the area or the computation time. The most popular AF is the log-sigmoid function, which has different possibilities of realizing in digital hardware. Equation approximation, Lookup Table (LUT) based approach and Piecewise Linear Approximation (PWL) are a few to mention. A two-fold approach to optimize the resource requirement is presented here. Primarily, Fixed-point computation (FXP) that needs minimal hardware, as against floating-point computation (FLP) is followed. Secondly, the PWL approximation of AF with more precision is proved to consume lesser Si area when compared to LUT based AF. Experimental results are presented for computation.

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2008

N Mohankumar, Bhuvan, Bb, NirmalaDevi, Mc, and Arumuga, Sd, “A Modified Genetic Algorithm for Evolution of Neural Network in Designing an Evolutionary Neuro-Hardware”, Proceedings of the 2008 International Conference on Genetic and Evolutionary Methods, GEM 2008. Las Vegas, NV, pp. 108-111, 2008.[Abstract]


Artificial Neural Networks (ANN) are inherently parallel architectures which can be implemented in software and hardware. One important implementation issue is the size of the neural network and its weight adaptation. This makes the hardware implementation complex and software learning slower. In practice Back propagation Neural Network is used for weight learning and evolutionary algorithm for network optimization. In this paper a modified genetic algorithm with more fondness to mutation is introduced to dynamically evolve network structure and weights at the same time. A single layered feed forward neural network is designed and trained using conventional method initially, then the proposed mutation based modified genetic algorithm is applied to evolve the weight matrix and structure pruning of the neural network. This algorithm facilitates the hardware implementation of ANN.

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Publication Type: Conference Paper

Year of Conference Title

2015

N. Devi M. R, ,, G. Sabari, A., Krishna, D. Ravi, Prasathe, A., Harish, K., and N Mohankumar, “Malicious Circuit Detection for Improved Hardware Security”, in The Third International Symposium on Security in Computing and Communications (SSCC’15), 2015.

2014

N Mohankumar, Ramesh, V. Ravikumar, Paramasivan, D., Ramya, H., and Raghavan, R., “Low Power Fault-Tolerant Reversible Full Adders”, in International Conference on Communication and Computing (ICC2014), 2014.

2011

D. Badarinath, Scaria, A., Devi, M. N., and N Mohankumar, “A compressed domain dual video watermarking for real-time applications”, in Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011, Coimbatore, 2011.[Abstract]


Main objective of dual video watermarking is to achieve better compression rates, robustness against attacks and high security which has been rarely reported. In this paper, visible and invisible watermark is embedded in the video encoder during compression, resulting in an optimized compression/ watermarking algorithm and system. Due to its lower complexity, Discrete Cosine Transform (DCT) watermarking is chosen here. Exhaustive simulations made on recovered watermark had high correlation after different attacks. This algorithm is suitable for in real-time digital video broadcasting and emerging applications such as video fingerprinting. More »»

2011

A. Scaria, D. Nath, B., Dr. Nirmala Devi M., and N Mohankumar, “Hardware implementation of svd based colour image watermarking in wavelet domain”, in Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011, Coimbatore, 2011.[Abstract]


While it has become very easy to process and store digital images effectively, it has also paved way for ease in illegal production and redistribution. Watermarking is the best way to protect digital image against illegal recording and distribution. From the literature survey, it has been affirmed that the frequency domain techniques are more robust than spatial domain techniques. In this paper a singular value decomposition (SVD) based watermarking is executed in wavelet domain. This paper proposes the design and hardware implementation of a fast RGB to YUV converter by standard NTSC conversion and reconstruction formulae using optimal 2-D systolic arrays for matrix multiplication.The scheme have been implemented in Altera Cyclone II FPGA. The hardware implementation of 2D DWT decomposition and IDWT reconstruction were implemented in Xilinx xc3s1000-4fg320. Watermarks inserted in the lowest frequencies (LL subband) are resistant to certain group of attacks, and watermarks embedded in highest frequencies (HH subband) are resistant to another group of attacks. Embedding the same watermark in all 4 blocks, will make it extremely difficult to remove or destroy the watermark from all frequency subbands. The proposed algorithm is less resilient to geometric distortion including rotation, scaling and translation. The hardware implementation watermarking schemes has advantages over the software implementation in terms of high performance, and reliability. A hybrid SVD image watermarking in wavelet domain, will have more robustness. © 2011 IEEE.

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