Qualification: 
M.E, BE
senthilmurugan@am.amrita.edu

Senthil Murugan has a Bachelor of Engineering in Electronics and Communication Engineering from Madras University, India and a Master of Engineering from Anna University, India.

He has worked for more than 12 years in the VLSI industry, 10 of which have been in the US. He served as Verification Engineer in Cirrus Logic Inc., USA and Senior Design Engineer in Onspec Electronics, TPL Gropus and Ironkey USA. He has extensive experience in design and verification in ASICs, FPGAs, and Systems for mass storage area.

Currently he is working as a senior Assistant Professor in ECE department of Amrita Vishwa Vidyapeetham, Amritapuri, India. He has taped out several designs (IDE & Flash memory based applications) during his tenure in VLSI Industry. His areas of expertise are FPGA & ASIC based system design, digital designs and embedded systems.

Publications

Publication Type: Journal Article

Year of Publication Publication Type Title

2015

Journal Article

T. C. Sruthi and Senthil Murugan, “Efficient implementation of image smoothing in FPGA”, International Journal of Applied Engineering Research, vol. 10, pp. 663-665, 2015.[Abstract]


Image smoothing has been extensively used for image processing applications such as image restoration. It is used in graphic processing units(GPU) and computer graphics. These GPU’s are used in embedded systems, mobile phones, personal computers and game consoles. Smoothing technique is done using Gaussian filter. In this project non- separable Gaussian smoothers are implemented on an FPGA platform. The use of adder tree makes it area efficient, computationally efficient and fast. So it is observed that for large size images the proposed Gaussian smoother implementation is efficient than the recent one. The architecture is coded in Verilog HDL and the whole design code is synthesized in Xilinx Virtex-5 FPGA, XC5VLX110T-1FF1136. © Research India Publications.

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2015

Journal Article

D. Jose and Senthil Murugan, “Verilog implementation of low density parity check codes”, International Journal of Applied Engineering Research, vol. 10, pp. 630-633, 2015.[Abstract]


Low Density Parity Check Codes (LDPC) are forward error correcting codes that is used for transmission of messages over noisy communication channel. These are linear error correcting code and finding application in highly efficient transfer of messages over noisy channel. LDPC codes are usually defined by sparse parity check matrix which is usually randomly generated. LDPC codes are capable of performing close to Shannon capacity. The major uses of LDPC codes are in digital video broadcasting (DVB) standard and are being seriously considered in various real-life, magnetic storage, 10 Gb Ethernet, and high-throughput wireless local area network. In this Paper LDPC encoder and decoder architecture will be designed using verilog code. The algorithm that is used here is hard decision decoding algorithm. © Research India Publications.

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