Publication

Abstract : Multipliers are key components in digital signal processors, where there is a high demand for high-speed hardware. The multiplier's performance is typically assessed using three main factors: speed, power and area. The new Vedic Multiplier uses a Speed Efficient Carry Select Adder (CSA) to improve the speed and also consume less power in the multiplication process. The Crosswise and Vertical Multiplication algorithm breaks down the input values into smaller segments, which are then multiplied by using the algorithm to produce partial output. The conclusive result is generated by adding these partial outputs with the help of CSA. In this project, a 16-bit Vedic Multiplier is created using Verilog HDL by incorporating CSA, half adders and full adders. The simulation is done using ModelSim and the design is synthesized using Cadence Genus. The proposed methodology has reduced delay by 8.6% and also reduced power consumption by 24.55% results compared to conventional CSA.