Publication

Abstract : As device dimensions are shrinking at a very fast pace in compliance with Moore’s law, it becomes extremely important to analyze and research any possibility of optimization in terms of the device parameters (area, power, and delay). One of the most important challenges affecting the performance of the Network on Chip Router is head-of-line (HOL) blocking, which hinders packet flow and compromises the speed of data flow. The concept of swapping the blocking head packet to release the blockage in the head position provided a feasible solution. However, this solution comes at the cost of increasing the area due to the additional requirement for buffer hardware to enable swapping and corresponding switch allocation. In a parallel directive, ensuring the functional correctness of Network on Chip (NoC) during post-silicon validation is extremely important. To execute this, Design for Debug (DFD) hardware is incorporated into the NoC routers which provides higher visibility and observability. However, these structures become redundant post validation and during normal operation but still add to the device area. The Optimized Network on Chip Buffer (ONoC Buf) proposes to reuse the trace buffer, which is a DFD component. This is used to assist with the input buffer virtual channel requirement of the NoC. This enables smaller virtual channels on the input side while allowing the removal of HoL blocking. It is further proposed to enable the packets stored in the trace buffers to participate in Switch Allocation (SA) along with those from virtual channels. This helps to increase the hit rate of SA. Experiment results show that the proposed ONoC Buf provides an improvement in switch allocation at a minimal area overhead. With the proposed design, a considerable improvement of approximately 32% is achieved in the delay parameter. This is made possible by reusing the trace buffer to extend the virtual channel at the input buffer. This is realized with a minimal increase of around 6.1% and 5.3% in area and power, respectively.