Publication

Abstract : In recent years, several embedded applications have made use of Multiply-ACcumulate (MAC) units, from signal processing to artificial intelligence. The basic blocks of MAC units are Multiplier, Adder, and Accumulator. The design and performance of MAC units are crucial because they directly affect the speed, power consumption, and total computing capability of the systems in which they are utilized. In the proposed work, a low-power MAC unit architecture is designed. Two-Stage Carry Select Adder (TSCSA) uses two types of cells which are 2:1 Multiplexer and NAND gates are used for adder design and Optimized Counter-Based Multiplier (OCBM) is used for multiplier design in MAC units. The experiment's findings indicate that, in comparison to the current MAC unit architecture, the suggested solution uses a 29.3% reduction in power, a 6.48% reduction in area, and a 3.34% reduction in delay.