Publication

Abstract : The critical charge of vulnerable nodes drops with technology scaling down, increasing the likelihood of soft mistakes in SRAM cells used in the aerospace sector. Active scaling of transistors is being done to improve operating speed, minimize power dissipation, and increase integration density. Sensitive nodes’ critical charge has decreased due to this tendency. Highly stable Soft Error Aware-14T (SEA-14T) and Soft Error Aware-16T (SEA-16T) SRAM cells are designed to reduce soft errors in the aerospace industry. Based on many criteria, this article compares two SRAM cells, SEA-16T and SEA-14T. The aerospace sector is the primary user of both of these soft error-aware SRAMs. Cadence Virtuoso Design suite with 45 nm technology is used to design, simulate, and analyze the performance of SEA-14T and SEA-16T SRAM cells. The performance analysis indicates that the read latency and write latency of SEA-16T are 68.75% and 37.5% more than SEA-14T respectively. SEA-16T consumes more power compared to SEA14T. Stability-wise SEA-16 T is more stable than SEA-14T which can be confirmed using parameters like read stability and write stability. SEA-16T shows an increase of 88.9% in read stability and 33.33% in write stability compared to SEA-14T. So, for stability-concerned applications, SEA-16T is a better choice.