Publication

Abstract : In the realm of computation, the demand for high-performance, energy-efficient computer devices is always rising. These devices require large-scale multiplier circuits; accurate multipliers consume valuable resource space, with increased power and delay. Approximate multipliers are used in applications where a certain level of error or approximation is acceptable, such as Computer Vision, DSP applications, Machine Learning and Artificial Intelligence. This work presents an implementation of an 8-bit approximate multiplier using a modified Wallace tree design that combines full adders, half adders, and 4-2 approximate compressors. The 4-2 approximate compressor proposed here has been done after thorough examination of multiple previously existing compressor designs. The design is implemented as Semi-Custom ASIC process, using Cadence Genus synthesis tool to obtain power and area reports. Finally, it is found that the proposed compressor design has best performance when employed in an approximate multiplier.