Publication

Abstract : As basic components, optimizing the power consumption of flip-flops (FFs) can significantly reduce the power of digital systems. This study proposes a static flip-flop architecture that is designed with 22 transistors using a single-phased clocking scheme and has a precharge-free operation. This architecture is designed, implemented, and compared with some of the existing flip-flop architectures in terms of power, delay, power-delay-product (PDP), and maximum operating frequency. Cadence Virtuoso tool is used to design and implement the existing and proposed flip-flop architectures in 45nm technology with a supply voltage of 0.6 V and with same specifications for all the flip-flops. When compared to an existing static redundant precharge-free True Single Phase Clocked (TSPC) flip-flop, the total power consumption of the proposed flip-flop design is decreased by 14.73% and the power-delay-product (PDP) is decreased by 11.09%. The number of transistors used in the proposed flip-flop is 22 which is 18.51% lower as compared to 27 transistors in the existing redundant precharge-free static TSPC flip-flop design. Static flip-flops are highly stable and robust for low to moderate-frequency applications. A dynamic flip-flop architecture is also proposed which is suitable for high-frequency applications and is designed with 10 transistors and has very low power consumption and delay compared to static flip-flop designs but is not suitable for low-frequency applications.