Publication

Abstract : This project employs an innovative approach to design optimized saturated binary counters, such as (7, 3), (15, 4), and other variants, which rely on sorting networks and 4:2 exact compressors. Compressors and counters with high compression ratios are necessary to increase the multiplier process's efficiency. This paper considers odd-even merge sorting for designing counters for medium-range sorting networks using stage-wise pipelining. By determining the trade-off between bit width vs. parameter degradations for different bit ranges, the hardware complexity is optimized compared to bitonic sorting network-based counters. To generate the rearranged sequences in the proposed counter, the inputs of the counters are initially divided into two unequal segments which are then used as inputs for the odd-even merge sorting networks. By adopting this method, the construction of (7,3) counter using one-hot code sequences is achieved. The same process is used to construct (15,4) and (31,5) counters. To optimize 4:2 compressor, the 4:2 exact compressor is designed using NAND gates only. Xilinx Vivado is used to simulate the existing and proposed counters and compressors. The performance of the living and proposed counters and compressors are analyzed and compared using the Cadence Genus synthesis tool, where the technology used 45nm. The comparison results show that the proposed counters and compressors perform better than their equivalents regarding speed, power, and area efficiency. Furthermore, the study explores the impact of this method on a 16*16 exact multiplier, where the counters and compressors are employed for the summation of partial products. Compared to a multiplier using existing bitonic sorting network-based counters and compressors, the proposed approach demonstrates an 8.13% reduction in size and a 15% decrease in power consumption, highlighting its substantial performance improvements.