Publication

Abstract : In recent years, deep-learning models have become increasingly complex, leading to a surge in demand for specialized hardware accelerators. Long Short-Term Memory also known as LSTM, is an extensively used neural network for sequential data processing. This paper presents the design and implementation of a hardware accelerator for bi-directional LSTM (Bi-LSTM), op-timized for power consumption and performance improvements with respect to state-of-the-art FPGA-based accelerators. The accelerator uses column bypass multiplier based column-wise matrix-vector multiplication to avoid unnecessary computations on zero-valued input data and reduce the data dependency which enables higher parallelism leading to reduced overall compute time. The Bi-LSTM design is simulated to verify its functionality and synthesize it on a target Xilinx Zync-7000 FPGA. The results demonstrate that the proposed accelerator achieves lesser power consumption with an increased frequency by 23.45 % and a 5.45x increase in energy efficiency when compared to state-of-the-art hardware accelerators for Bidirectional LSTM.