Publication

Abstract : SRAM is used in cache memory which is in turn used in processor-based system for the fast access of the frequently used data. By mitigating vulnerabilities to attacks that exploit leakage currents or introduce errors, these cells can ensure the confidentiality and integrity of stored data. Hence any improvement in SRAM will impact on the performance of the processor-based system leading to the better device efficiency in real time. This work proposes a 7T SRAM cell employing a dual phased-write operation to minimise the inter-dependency between the power consumption of stored and written data striking a balance between robust security and efficient performance. This proposed design is implemented using Cadence Virtuoso with 45 nm CMOS Technology under a power supply of 500 mV. The average power and energy consumption is reduced by 35% when compared to existing 7T SRAM Cell. The RSNM and HSNM of the proposed design is increased by 1.63% and 2.27% when compared to the conventional 6T SRAM Cell.