Publication

Abstract : Applications in computer vision and image analysis, including object recognition and diagnostic imaging, are reliant on a fundamental competency in image segmentation. However, high-computation methods are occasionally exceeded by the energy economy and processing speed of typical CPU-based systems. To surpass these limitations, a hardware-accelerated picture segmentation method is introduced, leveraging the Alternating Direction Method of Multipliers (ADMM) technology, FPGA parallel processing, and sparse subset selection. ADMM algorithms are designed in high-level synthesis (HLS) C code for deployment on Xilinx Zynq UltraScale+ MPSoC. This approach simplifies hardware integration and maintains accuracy while reducing latency and improving energy efficiency. Significant energy savings and decreased execution times are indicated by experimental results, with FPGA achieving segmentation in 9 ms as opposed to 13 ms on a CPU, thereby proving the tremendous computational efficiency of FPGA-based solutions. These results demonstrate how hardware acceleration can enable scalable real-time applications in limited resources by overcoming computational constraints.