Publication Type:

Conference Paper

Source:

2013 International Conference on Information Communication and Embedded Systems (ICICES) (2013)

URL:

https://ieeexplore.ieee.org/abstract/document/6508309

Keywords:

addressing scheme, Algorithm design and analysis, associated angle generator logic, coordinate rotation digital computer algorithm, CORDIC, Digital arithmetic, dynamic power consumption, efficient FFT architecture, fast Fourier transform implementation, Fast Fourier transforms, FFT, Generators, Low Power, Memory management, modified CORDIC algorithm, Random access memory, read-only storage, registers, ROM usage, Vectors, VLSI

Abstract:

This paper presents a pipelined, reduced memory and low power CORDIC-based architecture for fast Fourier transform implementation. The proposed algorithm utilizes a new addressing scheme and the associated angle generator logic in order to remove any ROM usage for storing twiddle factors. CORDIC is implemented by a simple hardware through repeated shift-add operations Low power is achieved by the using the Coordinate Rotation Digital Computer algorithm in the place of conventional multiplication and furthermore, dynamic power consumption is reduced with no delay penalties.

Cite this Research Publication

A. Malashri and Paramasivam C., “Low power and memory efficient FFT architecture using modified CORDIC algorithm”, in 2013 International Conference on Information Communication and Embedded Systems (ICICES), 2013.